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公开(公告)号:CN105428264B
公开(公告)日:2018-06-22
申请号:CN201510462877.7
申请日:2015-07-31
Applicant: 富士电机株式会社
Inventor: 今井诚
IPC: H01L21/60
CPC classification number: H01L24/97 , H01L23/057 , H01L25/072 , H01L2224/32225 , H01L2224/32245 , H01L2224/45 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/48 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49 , H01L2224/49109 , H01L2224/73265 , H01L2224/78 , H01L2224/78315 , H01L2224/7855 , H01L2224/78611 , H01L2224/85 , H01L2224/85181 , H01L2224/85205 , H01L2224/85947 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/1203 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/2076 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20306 , H01L2924/20307 , H01L2224/05599 , H01L2224/85399 , H01L2224/83 , H01L2924/00
Abstract: 本发明提供一种能够抑制在切断的引线上产生尖端的半导体装置的制造方法。在半导体装置的制造方法中执行的引线键合工序中,对接合于导电性部件(1)的引线(2)的接合区域(3)以外的切断位置(4)进行半切断而形成切口(5),使切口(5)振动以在切断位置(4)切断引线(2)。由于引线(2)被半切断,因此能够降低切断时对导电性部件(1)的损伤。另外,通过使形成于引线(2)的切口(5)振动,从而切口(5)的附近产生疲劳,引线(2)因来自切口(5)的断裂而切断。因此,能够抑制在引线(2)的切断面(2a)产生(至少朝向导电性部件(1)侧的)尖端。
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公开(公告)号:CN104916609B
公开(公告)日:2018-02-02
申请号:CN201410450124.X
申请日:2014-09-05
Applicant: 东芝存储器株式会社
Inventor: 赤羽隆章
IPC: H01L23/488 , H01L21/607 , H01L21/67
CPC classification number: H01L2224/05553 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48 , H01L2224/4809 , H01L2224/48096 , H01L2224/4846 , H01L2224/48472 , H01L2224/49 , H01L2224/49171 , H01L2224/78 , H01L2224/78301 , H01L2224/78313 , H01L2224/85 , H01L2224/85181 , H01L2224/85205 , H01L2924/10161 , H01L2924/10253 , H01L2924/381 , H01L2224/48095 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
Abstract: 本发明提供一种抑制导线、焊垫间的开路、短路的产生的半导体装置及制造其的楔形接合装置。半导体芯片在第1方向排列有长方形的第1连接区域。电路基板在第1方向排列有第2连接区域。第1连接区域的第1及第2接合点和第2连接区域的第3接合点利用一导线而连接。第1及第2接合点在第1连接区域上,排列在与第1方向交叉的第2方向。第1接合点的长度方向朝向第2方向,在将连接第2接合点与第3接合点的方向作为第3方向的情形时,第2接合点的长度方向比第2方向更朝向第3方向。
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公开(公告)号:CN105023902B
公开(公告)日:2018-01-30
申请号:CN201510431505.8
申请日:2010-07-16
Applicant: 新日铁住金高新材料株式会社 , 日铁住金新材料股份有限公司
CPC classification number: C22C5/04 , C22C5/02 , C22C5/06 , C22C9/00 , H01L24/43 , H01L24/45 , H01L2224/05624 , H01L2224/4312 , H01L2224/4321 , H01L2224/43848 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/4516 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45664 , H01L2224/48011 , H01L2224/48247 , H01L2224/48471 , H01L2224/4851 , H01L2224/48624 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48764 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/78301 , H01L2224/85045 , H01L2224/85065 , H01L2224/85075 , H01L2224/85181 , H01L2224/85186 , H01L2224/85207 , H01L2224/85439 , H01L2224/85444 , H01L2224/85464 , H01L2224/85564 , H01L2924/00011 , H01L2924/00015 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/01034 , H01L2924/01005 , H01L2924/01015 , H01L2924/01046 , H01L2924/01047 , H01L2924/0102 , H01L2924/01013 , H01L2924/00014 , H01L2224/45144 , H01L2924/01204 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/01001 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/01028 , H01L2924/0105 , H01L2924/01007 , H01L2224/45669 , H01L2924/2076 , H01L2924/01018 , H01L2224/48465 , H01L2924/20654 , H01L2924/20652 , H01L2924/20655 , H01L2924/00 , H01L2924/013 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/01004 , H01L2924/01033
Abstract: 本发明提供即使对于镀钯的引线框也能够确保良好的楔接合性、耐氧化性优异的以铜或铜合金为芯线的半导体用接合线。根据一个实施方式的半导体用接合线,其特征在于,具有:由铜或铜合金构成的芯线;形成于该芯线的表面的具有10~200nm的厚度的含有钯的被覆层;和形成于该被覆层的表面的具有1~80nm的厚度的含有金和钯的合金层,所述合金层中的金的浓度为10体积%~75体积%,在测定接合线表面的结晶取向所得到的测定结果中,相对于拉丝方向的倾斜为15度以下的结晶取向 的晶粒的面积比为40%~100%。
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公开(公告)号:CN103247589B
公开(公告)日:2017-10-20
申请号:CN201310049396.4
申请日:2013-02-07
Applicant: 三星电子株式会社
IPC: H01L23/488 , H01L21/60 , H01L25/065
CPC classification number: H01L24/85 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/4809 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/48616 , H01L2224/48624 , H01L2224/48992 , H01L2224/48997 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/85365 , H01L2224/85416 , H01L2224/85951 , H01L2224/85986 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/48455
Abstract: 本发明提供一种半导体封装件和制造半导体封装件的方法。该半导体封装件包括:包括板焊盘的板;安装在板上的多个半导体芯片,半导体芯片包括芯片焊盘。突起分别设置在芯片焊盘上,引线设置在芯片焊盘和突起之间。引线将多个半导体芯片的芯片焊盘和板焊盘彼此电连接。
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公开(公告)号:CN103794586B
公开(公告)日:2017-08-25
申请号:CN201410025484.5
申请日:2012-02-09
Applicant: 嘉盛马来西亚公司
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L24/45 , H01L23/4952 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/48137 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/4848 , H01L2224/78301 , H01L2224/85045 , H01L2224/85051 , H01L2224/8518 , H01L2224/85181 , H01L2224/85186 , H01L2224/85205 , H01L2224/85986 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/00 , H01L2924/20752 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
Abstract: 本发明涉及短的和低的回路丝线键合,一种多管芯封装包括各自具有其上布置有多个键合焊垫(106a/b,206a/b,406a/b,506a/b,706a/b)的上表面的第一半导体管芯和第二半导体管芯。第二半导体管芯的上表面可以是与第一半导体管芯的上表面一起基本上共同延伸的并且基本上沿平面延伸。多管芯封装还包括多根键合丝线(102,202,402),每根键合丝线将在第一半导体管芯的上表面上的键合焊垫之一耦接至在第二半导体管芯的上表面上的对应的一个键合焊垫。该多根键合丝线中的键合丝线具有布置于平面上方的一高度处的扭折(114,414,418,514,518),布置于第一半导体管芯与扭折之间的第一凸点(112,116,412,416,512,516),以及布置于第二半导体管芯与扭折之间的第二凸点。
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公开(公告)号:CN106558566A
公开(公告)日:2017-04-05
申请号:CN201610825014.6
申请日:2016-09-14
Applicant: 瑞萨电子株式会社
Inventor: 利根川丘
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L23/5283 , H01L21/31 , H01L21/31056 , H01L21/311 , H01L21/31116 , H01L21/44 , H01L23/3171 , H01L23/481 , H01L23/4827 , H01L23/522 , H01L23/528 , H01L23/53223 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/84 , H01L24/85 , H01L29/1095 , H01L29/417 , H01L29/66348 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L2224/02126 , H01L2224/02145 , H01L2224/0215 , H01L2224/02206 , H01L2224/02215 , H01L2224/031 , H01L2224/0345 , H01L2224/03464 , H01L2224/03522 , H01L2224/04034 , H01L2224/04042 , H01L2224/05007 , H01L2224/05017 , H01L2224/05023 , H01L2224/05025 , H01L2224/05027 , H01L2224/05083 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05558 , H01L2224/05562 , H01L2224/05568 , H01L2224/05582 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/29339 , H01L2224/32245 , H01L2224/37147 , H01L2224/45147 , H01L2224/48247 , H01L2224/48463 , H01L2224/48799 , H01L2224/48844 , H01L2224/73265 , H01L2224/8385 , H01L2224/84801 , H01L2224/85045 , H01L2224/85181 , H01L2224/85203 , H01L2924/05042 , H01L2924/0509 , H01L2924/05442 , H01L2924/07025 , H01L2924/1203 , H01L2924/1206 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/35121 , H01L2924/00014 , H01L2924/013 , H01L2924/01014 , H01L2924/01029 , H01L2924/00013 , H01L2924/059 , H01L2924/0103 , H01L2924/00 , H01L24/02 , H01L2224/02125 , H01L2224/03013 , H01L2224/03019 , H01L2224/04
Abstract: 本发明涉及一种半导体装置和制造半导体装置的方法。半导体装置的特性得到改善。半导体装置被配置为具有设置在互连上方并且具有开口的保护膜和设置在开口中的镀敷膜。将狭缝设置在开口的侧面中,并且将镀敷膜还配置在狭缝中。由此,将镀敷膜设置在开口的侧面中,并且镀敷膜还生长在狭缝中。这导致了在随后的镀敷膜的形成期间的长的镀敷溶液渗透路径。因此,在互连(焊盘区)中不容易形成腐蚀部分,即使形成了腐蚀部分,狭缝的部分也作为牺牲物先于互连(焊盘区)被腐蚀,使得可以抑制腐蚀部分向互连(焊盘区)中的扩展。
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公开(公告)号:CN102593333B
公开(公告)日:2016-11-23
申请号:CN201110348598.X
申请日:2011-11-07
Applicant: 三星电子株式会社
CPC classification number: H01L33/62 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/4809 , H01L2224/48247 , H01L2224/48465 , H01L2224/78268 , H01L2224/78301 , H01L2224/85045 , H01L2224/85181 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/12044 , H01L2924/181 , H01L2933/0066 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599
Abstract: 本发明公开一种发光装置封装及其制造方法,该发光装置封装包括:其上设置有安装部和端子部的封装本体;安装在安装部上的发光装置芯片;电连接发光装置芯片的电极和端子部的接合线。该接合线包括从发光装置芯片上升至环峰的上升部以及连接环峰和端子部的延伸部。上升部上设置有沿着与上升部上升的方向相交的方向弯曲的第一弯折部。
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公开(公告)号:CN103531494B
公开(公告)日:2016-08-24
申请号:CN201310271753.1
申请日:2013-07-01
Applicant: 库利克和索夫工业公司
IPC: H01L21/607
CPC classification number: H01L2224/78 , H01L2224/78301 , H01L2224/85 , H01L2224/85181 , H01L2224/85205 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: 一种调整引线键合机上的无空气球形成参数的方法,包括以下步骤:(a)提供参考无空气球接触高度;(b)测量引线键合机上的至少一个无空气球的受检无空气球接触高度;以及(c)如果所述受检无空气球接触高度与所述参考无空气球接触高度之间的差大于预定容限水平,则至少部分基于所述差来调整所述引线键合机上的无空气球形成参数。
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公开(公告)号:CN103339719B
公开(公告)日:2016-03-16
申请号:CN201280007491.1
申请日:2012-12-12
Applicant: 田中电子工业株式会社
IPC: H01L21/60
CPC classification number: H01L24/45 , H01B1/026 , H01L24/05 , H01L24/43 , H01L2224/04042 , H01L2224/05624 , H01L2224/43 , H01L2224/4321 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/45572 , H01L2224/45573 , H01L2224/45644 , H01L2224/45655 , H01L2224/45664 , H01L2224/45669 , H01L2224/48227 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85181 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2924/00011 , H01L2924/01006 , H01L2924/01015 , H01L2924/01047 , H01L2924/10252 , H01L2924/10253 , H01L2924/12041 , H01L2924/181 , H01L2924/01202 , H01L2924/01203 , H01L2924/20751 , H01L2924/20752 , H01L2924/00 , H01L2924/00015 , H01L2924/01008 , H01L2924/013 , H01L2924/00014 , H01L2924/01029 , H01L2924/00013 , H01L2924/01028 , H01L2924/01027 , H01L2924/01204 , H01L2924/01205 , H01L2924/01206 , H01L2924/0105 , H01L2924/0104 , H01L2924/01023 , H01L2924/01005 , H01L2924/01022 , H01L2224/45565 , H01L2924/01001 , H01L2924/01004 , H01L2924/01033
Abstract: 本发明提供一种球焊用被覆钯的铜线,其能够提高对铝电极的接合可靠性。本发明的球焊用被覆钯的铜线中,在钯中间层表面形成包含厚度为5nm以下的极薄层的金层,在含氢的不活泼气氛中进行热处理,中间层的钯侵入到金极薄层,通过微细的金相和钯相进行三维生长的层岛混合模式生长,形成金-钯混杂层。在热处理过程中,钯吸收氢,在热处理后进行骤冷,由此使上述混杂层的钯稳定化,在熔融焊球形成时尽快熔化,随着被覆线端面的金到达端面的钯熔化,均匀微细地分散到熔融焊球表面层,抑制与铝的接合界面中的铝的氧化。
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公开(公告)号:CN103367337B
公开(公告)日:2016-03-02
申请号:CN201210211291.X
申请日:2012-06-21
Applicant: 富士通天株式会社
CPC classification number: H01L2224/27013 , H01L2224/32225 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48483 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85051 , H01L2224/85181 , H01L2224/85186 , H01L2924/00014 , H01L2924/1423 , H01L2924/15153 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
Abstract: 一种半导体装置以及半导体装置的制造方法,能抑制成本并提高传输性能。半导体装置具有:电路基板(11)、MMIC芯片(121)、传输线路(13a)~(13o)、第一引线(W1)~(W12)和第二引线(W13)~(W15)。MMIC芯片(121)设置在电路基板(11)上。传输线路(13a)~(13o)形成在电路基板(11)上且与MMIC芯片(121)连接。第一引线(W1)~(W12)是一端与MMIC芯片(121)的端子接合之后,另一端与传输线路(13a)~(13l)的端子接合的引线。第二引线(W13)~(W15)是一端与传输线路(13m)~(13o)的端子接合之后,另一端与MMIC芯片(121)的端子接合的引线。
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