公开(公告)号：US09589839B1

公开(公告)日：2017-03-07

申请号：US15012082

申请日：2016-02-01

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii ,  Kengo Kajiwara ,  Seiji Shimabukuro ,  Akira Matsudaira ,  Hiroyuki Ogawa

IPC: H01L29/792 ,  H01L21/768 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76888 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.

Abstract translation: 可以通过采用组成调制的牺牲材料层来减轻替代电极集成方案中的导电层的圆角化。 绝缘层和组成调制的牺牲材料层的交替堆叠可以形成在衬底上。 每个组成调制的牺牲材料层具有材料成分的垂直调制，使得每个成分调制的牺牲材料层在其上部和下部比在其中间部分处的转化成比含氧化硅材料提供更大的阻力 随后的氧化过程。 鸟的喙特征可以形成较小的尺寸，并且通过用导电材料替换牺牲材料层的剩余部分而形成的导电层可以具有较少的圆角。 减少角落四舍五入可以提高三维存储设备的控制门的有效性。

公开(公告)号：US09419012B1

公开(公告)日：2016-08-16

申请号：US14744322

申请日：2015-06-19

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Seiji Shimabukuro ,  Tomoyuki Obu ,  Ryusuke Mikami

IPC: H01L27/115 ,  H01L21/768 ,  H01L29/16 ,  H01L29/04 ,  H01L21/311 ,  H01L29/792 ,  H01L29/788 ,  H01L23/522 ,  H01L29/423 ,  H01L21/28 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76831 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788

Abstract: Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling between neighboring electrically conductive gate electrodes. An alternating stack of first material layers and second material layers can be provided. After replacing the second material layers with electrically conductive layers, the first material layers can be removed to form cavities between the electrically conductive layers. A dielectric material can be deposited with high anisotropic deposition rate to form an insulating spacer. For example, a plasma assisted atomic layer deposition process can be employed to deposit a dielectric spacer that include laterally protruding portions that encapsulate the cavities at each level between neighboring pairs of electrically conductive layers. A contact via structure can be formed in the insulating spacer to provide electrical contact to a source region.

Abstract translation: 用于纵向存储器件的控制栅电极的导电层可以由空腔垂直间隔以减小相邻的导电栅电极之间的电容耦合。 可以提供第一材料层和第二材料层的交替堆叠。 在用导电层代替第二材料层之后，可以去除第一材料层以在导电层之间形成空腔。 可以以高各向异性沉积速率沉积电介质材料以形成绝缘间隔物。 例如，可以采用等离子体辅助原子层沉积工艺来沉积介电间隔物，其包括在相邻的导电层对之间的每个层级处封装空腔的横向突出部分。 可以在绝缘间隔物中形成接触通孔结构以提供与源极区域的电接触。

公开(公告)号：US09305937B1

公开(公告)日：2016-04-05

申请号：US14519733

申请日：2014-10-21

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Masanori Tsutsumi ,  Hiroshi Sasaki ,  Hiroyuki Ogawa ,  Michiaki Sano ,  Masato Miyamoto ,  Kensuke Yamaguchi ,  Seiji Shimabukuro

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Abstract translation: 提供了一种使存储器开口下面的半导体表面的过蚀刻或损坏最小化的方法。 第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。 牺牲衬垫形成在第一阻挡电介质层上。 通过牺牲衬垫的水平部分形成开口。 存储器开口底部的第一阻挡介电层的水平部分可以通过牺牲衬垫中的开口进行蚀刻。 衬底的半导体表面可以以最小的过蚀刻和/或表面损伤物理地暴露在存储器开口的底部。 可以在形成牺牲衬垫之前或之后形成第二阻挡电介质层，以提供多层阻挡电介质。

公开(公告)号：US09230972B1

公开(公告)日：2016-01-05

申请号：US14491026

申请日：2014-09-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Seiji Shimabukuro ,  Ryoichi Honma ,  Hiroyuki Ogawa ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: G11C16/04 ,  H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66 ,  G11C5/02 ,  H01L29/792

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

公开(公告)号：US20140353738A1

公开(公告)日：2014-12-04

申请号：US14464385

申请日：2014-08-20

Applicant: Sandisk Technologies Inc.

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Yao-Sheng Lee ,  Senaka Krishna Kanakamedala ,  Rahul Sharangpani ,  George Matamis ,  Johann Alsmeier ,  Seiji Shimabukuro ,  Genta Mizuno ,  Naoki Takeguchi

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.

Abstract translation: 一种制造单片三维NAND串的方法，包括在衬底上提供交替的第一材料层和第二材料层的堆叠。 第一材料层包括绝缘材料，第二材料层包括牺牲层。 该方法还包括在堆叠中形成背面开口，通过后侧开口选择性地去除第二材料层，以在相邻的第一材料层之间形成背侧凹槽，并在背侧凹槽和背侧开口内形成阻挡电介质。 阻挡电介质在后侧凹部内部具有蛤状区域。 该方法还包括在后侧凹部中在阻挡电介质的相应的蛤壳形区域中形成多个铜控制栅电极。

公开(公告)号：US09728499B2

公开(公告)日：2017-08-08

申请号：US14554685

申请日：2014-11-26

Applicant: SanDisk Technologies, Inc.

Inventor： Seiji Shimabukuro ,  Hiroaki Iuchi ,  Michiaki Sano ,  Naoki Takeguchi

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.

公开(公告)号：US09412749B1

公开(公告)日：2016-08-09

申请号：US14491026

申请日：2014-09-19

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Seiji Shimabukuro ,  Ryoichi Honma ,  Hiroyuki Ogawa ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: G11C16/04 ,  H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66 ,  G11C5/02 ,  H01L29/792

CPC classification number: H01L27/11556 ,  G11C5/02 ,  G11C16/0408 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract translation: 单片三维存储器件包括具有基本上平行于半导体衬底的主表面延伸的第一导电类型的主表面和掺杂阱区的半导体衬底，多个NAND存储器串，基本上垂直于半导体衬底的主表面延伸 所述半导体衬底以及基本上垂直于所述半导体衬底的主表面延伸的多个基本上柱状的支撑构件，每个支撑构件包括围绕导电芯材的电绝缘外部材料，所述导电芯材基本上垂直于所述半导体衬底的主表面延伸 半导体衬底并与掺杂阱区电接触。

公开(公告)号：US20160111439A1

公开(公告)日：2016-04-21

申请号：US14519733

申请日：2014-10-21

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Masanori Tsutsumi ,  Hiroshi Sasaki ,  Hiroyuki Ogawa ,  Michiaki Sano ,  Masato Miyamoto ,  Kensuke Yamaguchi ,  Seiji Shimabukuro

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Abstract translation: 提供了一种使存储器开口下面的半导体表面的过蚀刻或损坏最小化的方法。 第一隔离介电层通过交替的多个材料层和绝缘体层的堆叠形成在存储器开口中。 牺牲衬垫形成在第一阻挡电介质层上。 通过牺牲衬垫的水平部分形成开口。 存储器开口底部的第一阻挡介电层的水平部分可以通过牺牲衬垫中的开口进行蚀刻。 衬底的半导体表面可以以最小的过蚀刻和/或表面损伤物理地暴露在存储器开口的底部。 可以在形成牺牲衬垫之前或之后形成第二阻挡电介质层，以提供多层阻挡电介质。

公开(公告)号：US09159739B2

公开(公告)日：2015-10-13

申请号：US14464385

申请日：2014-08-20

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Yao-Sheng Lee ,  Senaka Krishna Kanakamedala ,  Rahul Sharangpani ,  George Matamis ,  Johann Alsmeier ,  Seiji Shimabukuro ,  Genta Mizuno ,  Naoki Takeguchi

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/7889 ,  H01L29/7926

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, and a plurality of copper containing control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located over the plurality of control gates, a tunnel dielectric in contact with the semiconductor channel, and at least one charge storage region located between the blocking dielectric and the tunnel dielectric.

Abstract translation: 单片三维NAND串包括半导体沟道，其中半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，以及多个含铜控制栅电极，其基本上平行于该衬底的主表面延伸 基质。 多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。 NAND串还包括位于多个控制栅极上的阻塞电介质，与半导体沟道接触的隧道电介质，以及位于阻挡电介质和隧道电介质之间的至少一个电荷存储区域。