公开(公告)号：US09911748B2

公开(公告)日：2018-03-06

申请号：US14867351

申请日：2015-09-28

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Masatoshi Nishikawa ,  Kiyohiko Sakakibara ,  Hiroyuki Ogawa ,  Shuji Minagawa

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/08 ,  H01L29/417 ,  H01L29/16 ,  H01L29/04 ,  H01L29/788 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/26513 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/7883

Abstract: An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening. After formation and subsequent removal of a dummy trench fill structure in the backside trench, a source region is formed by introducing dopants into the epitaxial pedestal structure.

公开(公告)号：US09589839B1

公开(公告)日：2017-03-07

申请号：US15012082

申请日：2016-02-01

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii ,  Kengo Kajiwara ,  Seiji Shimabukuro ,  Akira Matsudaira ,  Hiroyuki Ogawa

IPC: H01L29/792 ,  H01L21/768 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76888 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.

Abstract translation: 可以通过采用组成调制的牺牲材料层来减轻替代电极集成方案中的导电层的圆角化。 绝缘层和组成调制的牺牲材料层的交替堆叠可以形成在衬底上。 每个组成调制的牺牲材料层具有材料成分的垂直调制，使得每个成分调制的牺牲材料层在其上部和下部比在其中间部分处的转化成比含氧化硅材料提供更大的阻力 随后的氧化过程。 鸟的喙特征可以形成较小的尺寸，并且通过用导电材料替换牺牲材料层的剩余部分而形成的导电层可以具有较少的圆角。 减少角落四舍五入可以提高三维存储设备的控制门的有效性。

公开(公告)号：US09601508B2

公开(公告)日：2017-03-21

申请号：US14921385

申请日：2015-10-23

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Jongsun Sel ,  Chan Park ,  Atsushi Suyama ,  Frank Yu ,  Hiroyuki Ogawa ,  Ryoichi Honma ,  Kensuke Yamaguchi ,  Hiroaki Iuchi ,  Naoki Takeguchi ,  Tuan Pham ,  Kiyohiko Sakakibara ,  Jiao Chen

IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/16 ,  H01L29/7883

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

公开(公告)号：US09443866B1

公开(公告)日：2016-09-13

申请号：US14666789

申请日：2015-03-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Kiyohiko Sakakibara

IPC: H01L27/115 ,  H01L21/31 ,  H01L29/10 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  G11C16/04 ,  G11C16/06

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/0214 ,  H01L21/02326 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/7889 ,  H01L29/7926

Abstract: A tunneling dielectric layer for a vertical memory device is formed with a stack that provides a barrier height profile for high data retention tolerance. Memory stack structures extend through a stack of insulating layers and electrically conductive layers. Each memory stack structure comprises, from outside to inside, a blocking dielectric, memory elements, a tunneling dielectric layer, and a vertical semiconductor channel. The tunneling dielectric layer comprises, from outside to inside, an outer silicon oxide layer, a first silicon oxynitride layer having a first atomic nitrogen concentration, a second silicon oxynitride layer having a second atomic nitrogen concentration that is less than the first atomic nitrogen concentration, and an inner silicon oxide layer that contacts a vertical semiconductor channel. The reduced band gap of the first silicon oxynitride layer relative to the second silicon oxynitride layer provides additional energy barrier for relaxation of holes stored in the memory elements.

Abstract translation: 用于垂直存储器件的隧道电介质层由堆叠形成，其提供用于高数据保持容限的势垒高度分布。 存储器堆栈结构延伸穿过绝缘层和导电层的堆叠。 每个存储器堆叠结构包括从外部到内部的阻挡电介质，存储元件，隧道介电层和垂直半导体沟道。 隧道电介质层从外部到内部包括外部氧化硅层，具有第一原子氮浓度的第一氮氧化硅层，具有小于第一原子氮浓度的第二原子氮浓度的第二氮氧化硅层， 以及接触垂直半导体沟道的内部氧化硅层。 第一氧氮化硅层相对于第二氮氧化硅层的减小的带隙为存储在存储元件中的空穴的放松提供了额外的能量势垒。

公开(公告)号：US09666281B2

公开(公告)日：2017-05-30

申请号：US14707459

申请日：2015-05-08

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Kiyohiko Sakakibara

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: G11C16/0483 ,  G11C16/045 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42328 ,  H01L29/42344

Abstract: A p-i-n junction structure is formed within a memory film laterally surrounded by an alternating plurality of electrically insulating layers and electrically conductive layers to provide a three-dimensional memory structure. The p-i-n junction includes a lower junction between an intrinsic semiconductor channel portion and a lower doped semiconductor portion and an upper junction between the intrinsic semiconductor channel portion and an upper doped semiconductor portion. The memory film can be subsequently formed on a sidewall of the memory opening, and the intrinsic semiconductor channel portion can be deposited on the memory opening and the lower doped semiconductor portion. The upper doped semiconductor portion can be formed above a topmost electrically conductive layer. The lower doped semiconductor portion can provide hole charge carriers for electrical current.

公开(公告)号：US20160315095A1

公开(公告)日：2016-10-27

申请号：US14921385

申请日：2015-10-23

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Jongsun Sel ,  Chan Park ,  Atsushi Suyama ,  Frank Yu ,  Hiroyuki Ogawa ,  Ryoichi Honma ,  Kensuke Yamaguchi ,  Hiroaki Iuchi ,  Naoki Takeguchi ,  Tuan Pham ,  Kiyohiko Sakakibara ,  Jiao Chen

IPC: H01L27/115 ,  H01L29/16 ,  H01L21/311 ,  H01L29/788 ,  H01L21/28 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/16 ,  H01L29/7883

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

Abstract translation: 绝缘层和牺牲材料层的交替堆叠形成在衬底上。 在形成存储器开口之后，通过形成至少一个氧化硅部分，将存储器开口的所有表面设置为氧化硅表面。 在存储器开口中形成氮化硅层。 在形成存储器堆叠结构之后，可以使用氧化硅部分作为蚀刻停止来形成背面凹部。 随后可以使用氮化硅层作为蚀刻停止物去除氧化硅部分。 氮化硅层的物理暴露部分可以被选择性地移除到存储器堆叠结构。 可以通过连续使用蚀刻停止结构来最小化或消除对存储器堆叠结构的外层的损坏。 随后可以在背面凹槽中形成导电层。

公开(公告)号：US09356043B1

公开(公告)日：2016-05-31

申请号：US14746042

申请日：2015-06-22

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Kiyohiko Sakakibara ,  Shinsuke Yada

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region by forming a doped pocket region. The doped pocket region has the same conductivity type as a doped well that constitutes horizontal portions of the semiconductor channels that extend into the memory stack structures, and has a higher dopant concentration level than the doped well. The doped pocket region and a source region can be simultaneously formed by implanting p-type dopants and n-type dopants into a surface portion of the substrate underlying a backside contact trench. By selecting dopant species having different diffusion rates, the doped pocket region can surround the source region. The process parameters of the anneal process can be selected such that the interface between the dopant pocket region and the doped well underlies outermost memory stack structures.

Abstract translation: 三维存储堆叠结构中的垂直晶体管的阈值电压可以通过形成掺杂的穴区而与来自源区的横向距离无关。 掺杂的阱区具有与掺杂阱相同的导电类型，其构成延伸到存储堆叠结构中的半导体沟道的水平部分，并且具有比掺杂阱更高的掺杂剂浓度水平。 可以通过将p型掺杂剂和n型掺杂剂注入到在背面接触沟槽下面的衬底的表面部分中来同时形成掺杂的杂质区域和源极区域。 通过选择具有不同扩散速率的掺杂物种类，掺杂的杂质区可以包围源区。 可以选择退火工艺的工艺参数，使得掺杂剂袋区域和掺杂阱之间的界面位于最外层存储器堆叠结构之下。