公开(公告)号：US20150255481A1

公开(公告)日：2015-09-10

申请号：US14200426

申请日：2014-03-07

Applicant: SanDisk Technologies Inc.

Inventor： Matthias Baenninger ,  Johann Alsmeier ,  Akira Matsudaira ,  Jayavel Pachamuthu

IPC: H01L27/115 ,  H01L21/225 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/28282 ,  H01L21/02587 ,  H01L21/2251 ,  H01L21/306 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.

Abstract translation: 为3D堆叠的非易失性存储器件提供制造工艺，其提供源极接触到堆叠底部的存储器孔。 堆叠包括在衬底上的交替的控制栅极层和介电层，并且通过堆叠蚀刻存储器孔。 该过程避免了在存储器孔的底部蚀刻通过膜的需要。 相反，从存储孔的底部到堆叠的顶部形成路径。 路径包括使用衬底电介质中的空隙沟槽的水平部分和在堆叠中蚀刻的通道。 记忆膜，通道材料和电介质材料同时沉积在空隙和存储孔的整个内表面中。 该路径被填充金属以形成连续的低电阻导电路径。

公开(公告)号：US20150287733A1

公开(公告)日：2015-10-08

申请号：US14246656

申请日：2014-04-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Akira Matsudaira ,  Donovan Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L21/02164 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/7883

Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.

Abstract translation: 描述了在制造NAND闪速存储器和利用具有高纵横比的紧密间隔的器件结构的其它微电子器件时防止线塌陷的方法。 在一些实施例中，可以使用一个或多个机械支撑结构来在紧密间隔开的装置结构之间提供横向支撑，以防止在蚀刻过程（例如，在字线蚀刻期间）紧密间隔开的装置结构的折叠。 在一个示例中，在NAND快闪存储器的制造过程中，在执行高宽比字线蚀刻之前，一个或多个机械支撑结构可以就位，或者可以在字线蚀刻期间形成。 在一些情况下，一个或多个机械支撑结构可以包括在执行字线蚀刻之前就位的多晶硅间电介质（IPD）层的部分。

公开(公告)号：US09224746B2

公开(公告)日：2015-12-29

申请号：US14072222

申请日：2013-11-05

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Vinod R. Purayath ,  James Kai ,  Donovan Lee ,  Yuan Zhang ,  Akira Matsudaira

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/42324

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract translation: 一种非易失性存储器系统，包括具有在浮动栅极上具有倒T形的字线的非易失性存储装置。 倒T形形状具有较宽的底部部分和更薄的顶部部分。 较薄的顶部部分相对于较宽底部之间的间隔增加了相邻字线之间的间隔。 气隙可以分开相邻的字线。 字线的较薄顶部增加了相邻字线之间的路径长度。 可以通过减少相邻字线之间的电场来减小字线到字线短路的可能性。

公开(公告)号：US20140346583A1

公开(公告)日：2014-11-27

申请号：US14072222

申请日：2013-11-05

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Vinod R. Purayath ,  James Kai ,  Donovan Lee ,  Yuan Zhang ,  Akira Matsudaira

IPC: H01L27/115

CPC classification number: H01L27/11551 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11541 ,  H01L29/42324

Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.

Abstract translation: 一种非易失性存储器系统，包括具有在浮动栅极上具有倒T形的字线的非易失性存储装置。 倒T形形状具有较宽的底部部分和更薄的顶部部分。 较薄的顶部部分相对于较宽底部之间的间隔增加了相邻字线之间的间隔。 气隙可以分开相邻的字线。 字线的较薄顶部增加了相邻字线之间的路径长度。 可以通过减少相邻字线之间的电场来减小字线到字线短路的可能性。

公开(公告)号：US09553146B2

公开(公告)日：2017-01-24

申请号：US14297106

申请日：2014-06-05

Applicant: SanDisk Technologies Inc.

Inventor： Yanli Zhang ,  Matthias Baenninger ,  Akira Matsudaira ,  Yao-Sheng Lee ,  Johann Alsmeier

IPC: H01L29/792 ,  H01L29/10 ,  H01L27/115

CPC classification number: H01L29/1029 ,  H01L27/1157 ,  H01L27/11582

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.

Abstract translation: 单片三维NAND串包括半导体通道，其中半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个基本上平行于基板的主表面延伸的控制栅电极， 位于相邻的控制栅极之间的层间绝缘层，与多个控制栅电极接触的阻挡介电层和层间绝缘层，至少部分地与阻挡介电层接触的电荷存储层，以及隧道电介质 位于电荷存储层和半导体沟道之间。 电荷存储层具有弯曲轮廓。

公开(公告)号：US09552991B2

公开(公告)日：2017-01-24

申请号：US14265815

申请日：2014-04-30

Applicant: SanDisk Technologies, Inc.

Inventor： Akira Matsudaira ,  James Kai ,  Yuan Zhang ,  Vinod Purayath ,  Donovan Lee

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.

Abstract translation: 制造单片三维NAND串的方法包括在衬底上提供交替的第一材料层和不同于第一材料层的第二材料层的堆叠，蚀刻堆叠以在堆叠中形成至少一个沟槽，形成阻挡电介质 在所述至少一个沟槽的侧壁上方，在所述至少一个沟槽中的阻挡电介质上形成电荷存储层，在所述至少一个沟槽中的所述电荷存储层上形成隧道电介质，并在所述隧道上形成半导体通道 电介质在至少一个沟槽中。

公开(公告)号：US09209031B2

公开(公告)日：2015-12-08

申请号：US14200426

申请日：2014-03-07

Applicant: SanDisk Technologies Inc.

Inventor： Matthias Baenninger ,  Johann Alsmeier ,  Akira Matsudaira ,  Jayavel Pachamuthu

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/28282 ,  H01L21/02587 ,  H01L21/2251 ,  H01L21/306 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.

Abstract translation: 为3D堆叠的非易失性存储器件提供制造工艺，其提供源极接触到堆叠底部的存储器孔。 堆叠包括在衬底上的交替的控制栅极层和介电层，并且通过堆叠蚀刻存储器孔。 该过程避免了在存储器孔的底部蚀刻通过膜的需要。 相反，从存储孔的底部到堆叠的顶部形成路径。 路径包括使用衬底电介质中的空隙沟槽的水平部分和在堆叠中蚀刻的通道。 记忆膜，通道材料和电介质材料同时沉积在空隙和存储孔的整个内表面中。 该路径被填充金属以形成连续的低电阻导电路径。

公开(公告)号：US20150318298A1

公开(公告)日：2015-11-05

申请号：US14265815

申请日：2014-04-30

Applicant: SanDisk Technologies, Inc.

Inventor： Akira Matsudaira ,  James Kai ,  Yuan Zhang ,  Vinod Purayath ,  Donovan Lee

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.

Abstract translation: 制造单片三维NAND串的方法包括在衬底上提供交替的第一材料层和不同于第一材料层的第二材料层的堆叠，蚀刻堆叠以在堆叠中形成至少一个沟槽，形成阻挡电介质 在所述至少一个沟槽的侧壁上方，在所述至少一个沟槽中的阻挡电介质上形成电荷存储层，在所述至少一个沟槽中的所述电荷存储层上形成隧道电介质，并在所述隧道上形成半导体通道 电介质在至少一个沟槽中。

公开(公告)号：US09177808B2

公开(公告)日：2015-11-03

申请号：US14284917

申请日：2014-05-22

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Vinod R. Purayath ,  James Kai ,  Donovan Lee ,  Akira Matsudaira ,  Yuan Zhang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.

Abstract translation: 一个实施例涉及一种存储器件，其包括半导体通道，位于半导体通道上方的隧道电介质，位于隧道电介质上方的电荷存储区域，位于电荷存储区域上方的阻塞电介质，以及位于阻塞 电介质。 阻塞电介质和控制栅极之间的界面基本上防止氧气从阻挡电介质扩散到控制栅极中。

公开(公告)号：US20140346584A1

公开(公告)日：2014-11-27

申请号：US14284917

申请日：2014-05-22

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Vinod R. Purayath ,  James Kai ,  Donovan Lee ,  Akira Matsudaira ,  Yuan Zhang

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate.

Abstract translation: 一个实施例涉及一种存储器件，其包括半导体通道，位于半导体通道上方的隧道电介质，位于隧道电介质上方的电荷存储区域，位于电荷存储区域上方的阻塞电介质，以及位于阻塞 电介质。 阻塞电介质和控制栅极之间的界面基本上防止氧气从阻挡电介质扩散到控制栅极中。