Method of reducing control gate electrode curvature in three-dimensional memory devices
    1.
    发明授权
    Method of reducing control gate electrode curvature in three-dimensional memory devices 有权
    降低三维存储器件中控制栅电极曲率的方法

    公开(公告)号:US09589839B1

    公开(公告)日:2017-03-07

    申请号:US15012082

    申请日:2016-02-01

    Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.

    Abstract translation: 可以通过采用组成调制的牺牲材料层来减轻替代电极集成方案中的导电层的圆角化。 绝缘层和组成调制的牺牲材料层的交替堆叠可以形成在衬底上。 每个组成调制的牺牲材料层具有材料成分的垂直调制,使得每个成分调制的牺牲材料层在其上部和下部比在其中间部分处的转化成比含氧化硅材料提供更大的阻力 随后的氧化过程。 鸟的喙特征可以形成较小的尺寸,并且通过用导电材料替换牺牲材料层的剩余部分而形成的导电层可以具有较少的圆角。 减少角落四舍五入可以提高三维存储设备的控制门的有效性。

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