公开(公告)号：US20180315843A1

公开(公告)日：2018-11-01

申请号：US16029505

申请日：2018-07-06

Applicant: Transphorm Inc.

Inventor： Rakesh K. Lal

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L27/06 ,  H01L27/085 ,  H01L27/088 ,  H01L29/20 ,  H01L29/40 ,  H01L23/29 ,  H01L21/02 ,  H01L23/31 ,  H01L23/00 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

公开(公告)号：US10063138B1

公开(公告)日：2018-08-28

申请号：US15428726

申请日：2017-02-09

Applicant: Transphorm Inc.

Inventor： Liang Zhou ,  Yifeng Wu

IPC: H02M1/42

CPC classification number: H02M1/4208 ,  G01R19/0084 ,  G01R19/0092 ,  H02M1/4233 ,  H02M7/219 ,  Y02B70/126 ,  Y02P80/112

Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.

公开(公告)号：US10043896B2

公开(公告)日：2018-08-07

申请号：US15836157

申请日：2017-12-08

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

公开(公告)号：US20170222640A1

公开(公告)日：2017-08-03

申请号：US15491920

申请日：2017-04-19

Applicant: Transphorm Inc.

Inventor： Zhan Wang ,  Yifeng Wu ,  James Honea

IPC: H03K17/16 ,  H03K17/041 ,  H03K17/10 ,  H01L27/06 ,  H01L29/20 ,  H01L23/64 ,  H03K17/12 ,  H01L27/088

CPC classification number: H03K17/162 ,  H01L23/49562 ,  H01L23/552 ,  H01L23/645 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0883 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/3025 ,  H03K17/04106 ,  H03K17/102 ,  H03K17/122 ,  H03K17/16 ,  H03K17/165 ,  H03K2017/6875 ,  H01L2224/45099

Abstract: A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.

公开(公告)号：US09634100B2

公开(公告)日：2017-04-25

申请号：US14934565

申请日：2015-11-06

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Srabanti Chowdhury ,  Ilan Ben-Yaacov

IPC: H01L31/0328 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/78

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

公开(公告)号：US09590494B1

公开(公告)日：2017-03-07

申请号：US14802333

申请日：2015-07-17

Applicant: Transphorm Inc.

Inventor： Liang Zhou ,  Yifeng Wu

IPC: H02M7/06 ,  H02M1/42 ,  H02M7/217 ,  G01R1/20 ,  G01R19/00

CPC classification number: H02M1/4208 ,  G01R1/203 ,  G01R19/0092 ,  H02M1/4233 ,  H02M7/219 ,  Y02B70/126

Abstract: A power factor correction circuit comprises a pair of III-N based switches coupled to a first reference ground, and an inductive component connected in series with a current sensing resistor. A first side of the current sensing resistor is coupled to a second reference ground which is electrically isolated from the first reference ground, and a second side of the current sensing resistor is coupled to a control circuit. The control circuit is also coupled to the second reference ground and is configured to measure current flowing through the inductive component during operation of the power factor correction circuit.

Abstract translation: 功率因数校正电路包括耦合到第一参考地的一对基于III-N的开关和与电流感测电阻器串联连接的电感元件。 电流感测电阻器的第一侧耦合到与第一参考地电隔离的第二参考地，并且电流感测电阻器的第二侧耦合到控制电路。 控制电路还耦合到第二参考地，并且被配置为在功率因数校正电路的操作期间测量流过电感元件的电流。

公开(公告)号：US20170025267A1

公开(公告)日：2017-01-26

申请号：US15288120

申请日：2016-10-07

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L21/02 ,  H01L29/861 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract translation: 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US20160359030A1

公开(公告)日：2016-12-08

申请号：US15242266

申请日：2016-08-19

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/207 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09443938B2

公开(公告)日：2016-09-13

申请号：US14327371

申请日：2014-07-09

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L29/7783 ,  H01L29/045 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/51 ,  H01L29/66462

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract translation: 晶体管包括III-N层结构，其包含在III-N势垒层和p型III-N层之间的III-N沟道层。 晶体管还包括源极和漏极之间的源极，漏极和栅极，栅极在III-N层结构之上。 p型III-N层包括至少部分地在栅极和漏极之间的器件访问区域中的第一部分，并且p型III-N层的第一部分电连接到源极和电 从排水沟隔离。 当晶体管偏置为截止状态时，p型层可能导致器件访问区域中的沟道电荷随漏极电压增加而消耗，从而导致更高的击穿电压。

公开(公告)号：US09362903B2

公开(公告)日：2016-06-07

申请号：US14708627

申请日：2015-05-11

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Liang Zhou ,  Zhan Wang

IPC: H03K3/00 ,  H03K17/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H03K17/687

CPC classification number: H03K17/162 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/66522 ,  H01L29/7786 ,  H03K17/163 ,  H03K2017/6875

Abstract: An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.