公开(公告)号：US20160359030A1

公开(公告)日：2016-12-08

申请号：US15242266

申请日：2016-08-19

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/207 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09293458B2

公开(公告)日：2016-03-22

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06 ,  H03K17/567 ,  H01L23/495 ,  H01L25/16 ,  H01L23/64 ,  H01L25/18

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US09224671B2

公开(公告)日：2015-12-29

申请号：US14522154

申请日：2014-10-23

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  Yuvaraj Dora ,  Yifeng Wu ,  Umesh Mishra ,  Nicholas Fichtenbaum ,  Rakesh K. Lal

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L21/18 ,  H01L23/34 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L29/30 ,  H01L23/373

CPC classification number: H01L23/34 ,  H01L21/02118 ,  H01L21/0254 ,  H01L21/486 ,  H01L21/76254 ,  H01L23/3732 ,  H01L23/3738 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract translation: III-N器件用III-N层，其上的电极，与III-N层和电极相邻的钝化层，与钝化层和电极相邻的厚绝缘层，能够转移大量的高导热载体 远离III-N器件的热量，以及厚绝缘层和载体之间的结合层。 接合层将厚绝缘层附着到载体上。 厚的绝缘层可以具有精确控制的厚度并且是导热的。

公开(公告)号：US09041065B2

公开(公告)日：2015-05-26

申请号：US13973890

申请日：2013-08-22

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Umesh Mishra ,  Primit Parikh ,  Rongming Chu ,  Ilan Ben-Yaacov ,  Likun Shen

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872 ,  H01L27/06 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/0615 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract translation: 平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。 金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。 金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

公开(公告)号：US20140021934A1

公开(公告)日：2014-01-23

申请号：US13803912

申请日：2013-03-14

Applicant: Transphorm, Inc.

Inventor： Yifeng Wu ,  Primit Parikh

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/7787 ,  H02M3/155

Abstract: A circuit includes a switching device comprising a control terminal and first and second power terminals, and an inductive element having a first terminal electrically connected to the second power terminal of the switching device. The electronic circuit is configured such that in a first mode of operation, the control terminal of the switching device is biased off, current flows through the inductive element, and the switching device blocks a first voltage. In a second mode of operation, the control terminal of the switching device is biased off, and voltage blocked by the switching device decreases from the first voltage to a second voltage. In a third mode of operation, the control terminal of the switching device is biased on and the current flowing through the inductive element flows through the switching device.

Abstract translation: 电路包括开关装置，其包括控制端子和第一和第二电源端子，以及电感元件，其具有电连接到开关装置的第二电源端子的第一端子。 电子电路被配置为使得在第一操作模式中，开关装置的控制端被偏置，电流流过电感元件，并且开关装置阻塞第一电压。 在第二操作模式中，开关装置的控制端被偏置，并且由开关装置阻挡的电压从第一电压降低到第二电压。 在第三种操作模式中，开关装置的控制端被偏置，并且流过电感元件的电流流过开关装置。

公开(公告)号：US09171836B2

公开(公告)日：2015-10-27

申请号：US14478504

申请日：2014-09-05

Applicant: Transphorm Inc.

Inventor： Rakesh K. Lal ,  Robert Coffie ,  Yifeng Wu ,  Primit Parikh ,  Yuvaraj Dora ,  Umesh Mishra ,  Srabanti Chowdhury ,  Nicholas Fichtenbaum

IPC: H03K17/687 ,  H01L27/02 ,  H01L25/00 ,  H01L21/8236 ,  H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H03K17/10 ,  H01L29/423 ,  H01L29/872 ,  H01L29/20

CPC classification number: H01L27/0288 ,  H01L21/8236 ,  H01L25/00 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H03K17/102 ,  H03K2017/6875 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract translation: 电子部件包括耗尽型晶体管，增强型晶体管和电阻。 耗尽型晶体管具有比增强型晶体管更高的击穿电压。 电阻器的第一端子电连接到增强型晶体管的源极，并且电阻器的第二端子和耗尽型晶体管的源极电连接到增强型晶体管的漏极。 耗尽型晶体管的栅极可以电连接到增强型晶体管的源极。

公开(公告)号：US20140361309A1

公开(公告)日：2014-12-11

申请号：US14464639

申请日：2014-08-20

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Abstract translation: 一种III-N半导体器件，其包括衬底和包括部分在栅极区域下方的区域的氮化物沟道层，以及在栅极下方的部分的相对侧上的两个沟道存取区域。 通道接入区域可以在与栅极下方的区域不同的层中。 该器件包括与沟道层相邻的AlXN层，其中X是镓，铟或它们的组合，以及在与沟道接入区相邻的区域中与AlXN层相邻的优选n掺杂GaN层。 选择AlXN层中的Al的浓度，n掺杂GaN层中的AlXN层厚度和n掺杂浓度，以在沟道接入区域中引起2DEG电荷，而不在栅极下方引起任何实质的2DEG电荷，使得 在没有施加到栅极的开关电压的情况下，通道不导通。

公开(公告)号：US20140099757A1

公开(公告)日：2014-04-10

申请号：US14102750

申请日：2013-12-11

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  Yuvaraj Dora ,  Yifeng Wu ,  Umesh Mishra ,  Nicholas Fichtenbaum ,  Rakesh K. Lal

IPC: H01L21/02 ,  H01L21/48 ,  H01L29/66

CPC classification number: H01L23/34 ,  H01L21/02118 ,  H01L21/0254 ,  H01L21/486 ,  H01L21/76254 ,  H01L23/3732 ,  H01L23/3738 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract translation: III-N器件用III-N层，其上的电极，与III-N层和电极相邻的钝化层，与钝化层和电极相邻的厚绝缘层，能够转移大量的高导热载体 远离III-N器件的热量，以及厚绝缘层和载体之间的结合层。 接合层将厚绝缘层附着到载体上。 厚的绝缘层可以具有精确控制的厚度并且是导热的。

公开(公告)号：US20140042495A1

公开(公告)日：2014-02-13

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H01L27/088

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US20130316502A1

公开(公告)日：2013-11-28

申请号：US13954772

申请日：2013-07-30

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/66

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.