Invention Grant
- Patent Title: Method of reducing control gate electrode curvature in three-dimensional memory devices
- Patent Title (中): 降低三维存储器件中控制栅电极曲率的方法
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Application No.: US15012082Application Date: 2016-02-01
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Publication No.: US09589839B1Publication Date: 2017-03-07
- Inventor: Yusuke Ikawa , Kiyohiko Sakakibara , Eisuke Takii , Kengo Kajiwara , Seiji Shimabukuro , Akira Matsudaira , Hiroyuki Ogawa
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L21/768 ; H01L27/115 ; H01L23/522 ; H01L23/528

Abstract:
Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.
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