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公开(公告)号：US09082500B1
公开(公告)日：2015-07-14
申请号：US14487578
申请日：2014-09-16
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku
CPC classification number: G11C16/26 , G11C8/10 , G11C16/0433 , G11C16/08 , G11C16/28
Abstract: A non-volatile memory includes a memory array, a row decoder, a source line decoder, a column decoder, and a sensing circuit. The memory array is connected with m word lines, n source lines and n bit lines. The row decoder determines a selected row of n memory cells. The n memory cells in the selected row are connected with the n source lines and the n bit lines. By the source line decoder, an x-th source line is connected with a source line voltage but the other source lines of the n source lines are in a floating state. By the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines are connected with a reference voltage. The sensing circuit determines a storing state of a selected memory cell.
Abstract translation: 非易失性存储器包括存储器阵列，行解码器，源极线解码器，列解码器和感测电路。 存储器阵列与m个字线，n个源极线和n个位线连接。 行解码器确定n个存储单元的所选行。 所选行中的n个存储单元与n个源极线和n个位线连接。 通过源极线解码器，第x个源极线与源极线电压连接，但是n个源极线的其它源极线处于浮置状态。 通过列解码器，n位线的第x位线与数据线连接，而其它位线与参考电压连接。 感测电路确定所选择的存储单元的存储状态。
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公开(公告)号：US20200327945A1
公开(公告)日：2020-10-15
申请号：US16830296
申请日：2020-03-26
Applicant: eMemory Technology Inc.
Inventor： Ying-Je Chen , Wein-Town Sun , Wei-Ming Ku
Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.
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公开(公告)号：US20190372456A1
公开(公告)日：2019-12-05
申请号：US16365661
申请日：2019-03-26
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong
Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
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公开(公告)号：US20150200017A1
公开(公告)日：2015-07-16
申请号：US14487578
申请日：2014-09-16
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku
CPC classification number: G11C16/26 , G11C8/10 , G11C16/0433 , G11C16/08 , G11C16/28
Abstract: A non-volatile memory includes a memory array, a row decoder, a source line decoder, a column decoder, and a sensing circuit. The memory array is connected with m word lines, n source lines and n bit lines. The row decoder determines a selected row of n memory cells. The n memory cells in the selected row are connected with the n source lines and the n bit lines. By the source line decoder, an x-th source line is connected with a source line voltage but the other source lines of the n source lines are in a floating state. By the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines are connected with a reference voltage. The sensing circuit determines a storing state of a selected memory cell.
Abstract translation: 非易失性存储器包括存储器阵列，行解码器，源极线解码器，列解码器和感测电路。 存储器阵列与m个字线，n个源极线和n个位线连接。 行解码器确定n个存储单元的所选行。 所选行中的n个存储单元与n个源极线和n个位线连接。 通过源极线解码器，第x个源极线与源极线电压连接，但是n个源极线的其它源极线处于浮置状态。 通过列解码器，n位线的第x位线与数据线连接，而其它位线与参考电压连接。 感测电路确定所选择的存储单元的存储状态。
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公开(公告)号：US12283326B2
公开(公告)日：2025-04-22
申请号：US18113675
申请日：2023-02-24
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku
Abstract: A memory cell of a non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switching transistor and a second capacitor. A first drain/source terminal of the select transistor is connected with a source line. A gate terminal of the select transistor is connected with a word line. The two drain/source terminals of the floating gate transistor are respectively connected with a second drain/source terminal of the select transistor and a bit line. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. The two drain/source terminals of the switching transistor are respectively connected with the erase node and an erase line. The gate terminal of the switching transistor is connected with a control line. The second capacitor is connected between the erase node and a boost line.
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Patent Agency Ranking
公开(公告)号：US11557338B2
公开(公告)日：2023-01-17
申请号：US17319127
申请日：2021-05-13
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Wei-Ming Ku , Ying-Je Chen
Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.
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公开(公告)号：US11101798B2
公开(公告)日：2021-08-24
申请号：US16830296
申请日：2020-03-26
Applicant: eMemory Technology Inc.
Inventor： Ying-Je Chen , Wein-Town Sun , Wei-Ming Ku
IPC: G11C11/16 , H03K19/00 , H03K17/16 , H03K19/0185 , H03K3/356 , H03K19/0944 , G05F3/26 , H02M3/07 , H03K17/687 , G11C5/02 , G11C7/06 , G11C7/10 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/16
Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.
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公开(公告)号：US10693369B2
公开(公告)日：2020-06-23
申请号：US16365661
申请日：2019-03-26
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong
Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
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公开(公告)号：US20170206976A1
公开(公告)日：2017-07-20
申请号：US15397043
申请日：2017-01-03
Applicant: eMemory Technology Inc.
Inventor： Chih-Yang Huang , Wei-Ming Ku
IPC: G11C16/30
CPC classification number: G11C16/30 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11558 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
Abstract: A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. An output signal is outputted from the node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. The first supply voltage, the second supply voltage or the bias voltage is selected as the output signal.
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公开(公告)号：US20250157553A1
公开(公告)日：2025-05-15
申请号：US18882728
申请日：2024-09-11
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong , Chih-Yang Huang , Che-Wei Chang
Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.
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