公开(公告)号：US20250159879A1

公开(公告)日：2025-05-15

申请号：US18788920

申请日：2024-07-30

Applicant: eMemory Technology Inc.

Inventor： Wein-Town SUN ,  Hsueh-Wei CHEN

IPC: H10B41/35 ,  H01L29/423 ,  H01L29/788

Abstract: A non-volatile memory device including a substrate and a memory cell. The memory cell includes a select transistor, a floating gate transistor, and a metal conductor. The select transistor includes a select gate structure over the substrate, a first source/drain region on a first side of the select gate structure, and a second source/drain region on a second side of the select gate structure opposite the first side. The floating gate transistor includes a floating gate structure over the substrate, the second source/drain region on a third side of the floating gate structure, and a third source/drain region on a fourth side of the floating gate structure opposite the third side. The metal conductor is over and electrically isolated from the floating gate structure. The floating gate transistor further includes a first low-voltage lightly doped drain between the floating gate structure and the third source/drain region.

公开(公告)号：US12283326B2

公开(公告)日：2025-04-22

申请号：US18113675

申请日：2023-02-24

Applicant: eMemory Technology Inc.

Inventor： Wei-Ming Ku

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A memory cell of a non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switching transistor and a second capacitor. A first drain/source terminal of the select transistor is connected with a source line. A gate terminal of the select transistor is connected with a word line. The two drain/source terminals of the floating gate transistor are respectively connected with a second drain/source terminal of the select transistor and a bit line. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. The two drain/source terminals of the switching transistor are respectively connected with the erase node and an erase line. The gate terminal of the switching transistor is connected with a control line. The second capacitor is connected between the erase node and a boost line.

公开(公告)号：US12255645B2

公开(公告)日：2025-03-18

申请号：US18227409

申请日：2023-07-28

Applicant: eMemory Technology Inc.

Inventor： Chia-Jung Hsu ,  Chun-Yuan Lo ,  Chun-Hsiao Li ,  Chang-Chun Lung

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  H03K19/0185

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

公开(公告)号：US20250062765A1

公开(公告)日：2025-02-20

申请号：US18757441

申请日：2024-06-27

Applicant: eMemory Technology Inc.

Inventor： Dung Le Tan Hoang

IPC: H03K19/0185 ,  H03K3/356 ,  H03K19/00

Abstract: A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.

公开(公告)号：US20250024668A1

公开(公告)日：2025-01-16

申请号：US18670762

申请日：2024-05-22

Applicant: eMemory Technology Inc.

Inventor： Yi-Hung LI ,  Chun-Hung LIN

IPC: H10B20/25 ,  H01L29/417 ,  H01L29/78

Abstract: An antifuse-type memory includes a first memory cell. The first memory cell includes a first select transistor, a first following transistor and a first antifuse transistor. A first drain/source terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor. A gate terminal of the first following transistor is connected with a first following control line. The first antifuse transistor includes a first fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer. The first gate layer is connected with a first antifuse control line.

公开(公告)号：US20250023567A1

公开(公告)日：2025-01-16

申请号：US18660251

申请日：2024-05-10

Applicant: eMemory Technology Inc.

Inventor： Wei-Chiang ONG ,  Cheng-Yu CHUNG

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/356

Abstract: A level shifting circuit includes a first-type level shifter, a second-type level shifter and a controller. The controller is connected to the output terminal of the first-type level shifter and the output terminal of the second-type level shifter. The level shifting circuit can be operated in different modes. In a standby mode, the logic level state of an output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the first-type level shifter. In a non-standby mode, the logic level state of the output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the second-type level shifter.

公开(公告)号：US20240420745A1

公开(公告)日：2024-12-19

申请号：US18629972

申请日：2024-04-09

Applicant: eMemory Technology Inc.

Inventor： Wei-Ming KU

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/20

Abstract: A sense amplifier for a non-volatile memory is provided. A first memory cell of the non-volatile memory is coupled to a data line. The sense amplifier includes a first switching device, a first voltage boosting circuit and a comparator. A first terminal of the first switching device is connected with the data line. A second terminal of the first switching device is connected with a ground terminal. A control terminal of the first switching device receives a reset signal. An input terminal of the first voltage boosting circuit is connected with the data line. An output terminal of the first voltage boosting circuit is connected with a sensing node. A first input terminal of the comparator receives a comparison voltage. A second input terminal of the comparator is connected with the sensing node. An output terminal of the comparator generates an output data.

公开(公告)号：US20240395342A1

公开(公告)日：2024-11-28

申请号：US18417389

申请日：2024-01-19

Applicant: eMemory Technology Inc.

Inventor： Chia-Jung HSU ,  Yun-Jen Ting ,  Cheng-Heng Chung ,  Chun-Hsiao Li ,  Tsung-Mu Lai

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35 ,  H10B43/35

Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

公开(公告)号：US20240161844A1

公开(公告)日：2024-05-16

申请号：US18370412

申请日：2023-09-20

Applicant: eMemory Technology Inc.

Inventor： Chia-Fu CHANG ,  Jen-Yu PENG ,  Ming-Hsuan TAN

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.

公开(公告)号：US20240161843A1

公开(公告)日：2024-05-16

申请号：US18370404

申请日：2023-09-20

Applicant: eMemory Technology Inc.

Inventor： Chia-Fu Chang ,  Chun-Hung Lin ,  Jen-Yu Peng ,  You-Ruei Chuang

IPC: G11C17/18 ,  G11C7/08 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/08 ,  G11C17/16

Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.