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公开(公告)号：US11690221B2
公开(公告)日：2023-06-27
申请号：US17391041
申请日：2021-08-02
Applicant: eMemory Technology Inc.
Inventor： Wei-Chiang Ong , Tsung-Ta Hsieh , Chih-Yang Huang
IPC: G11C7/00 , H10B41/60 , G11C16/14 , G11C16/04 , G11C16/26 , G11C16/30 , H02M3/07 , H10B41/10 , H10B41/30
CPC classification number: H10B41/60 , G11C16/045 , G11C16/14 , G11C16/26 , G11C16/30 , H02M3/073 , H10B41/10 , H10B41/30
Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.
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Patent Agency Ranking
公开(公告)号：US20190372456A1
公开(公告)日：2019-12-05
申请号：US16365661
申请日：2019-03-26
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong
Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
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公开(公告)号：US10693369B2
公开(公告)日：2020-06-23
申请号：US16365661
申请日：2019-03-26
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong
Abstract: A voltage control device includes a first charge pump, a first power switch, a second charge pump, a second power switch, and a third power switch. The first charge pump generates a first application voltage according to the first system voltage. The first power switch has a first input terminal for receiving the first system voltage, a second input terminal for receiving the first application voltage, and an output terminal. The second charge pump generates a second application voltage according to a voltage received by the input terminal of the second charge pump. The second power switch has an input terminal for receiving the second application voltage, and an output terminal. The third power switch has a first input terminal coupled to the output terminal of the first charge pump, a second input terminal coupled to the output terminal of the second charge pump, and an output terminal.
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公开(公告)号：US20250157553A1
公开(公告)日：2025-05-15
申请号：US18882728
申请日：2024-09-11
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming Ku , Wei-Chiang Ong , Chih-Yang Huang , Che-Wei Chang
Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.
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公开(公告)号：US20250157545A1
公开(公告)日：2025-05-15
申请号：US18892600
申请日：2024-09-23
Applicant: eMemory Technology Inc.
Inventor： Wei-Chiang Ong
Abstract: A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.
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公开(公告)号：US10734083B2
公开(公告)日：2020-08-04
申请号：US16113265
申请日：2018-08-27
Applicant: eMemory Technology Inc.
Inventor： Yu Wu , Wei-Chiang Ong , Chih-Yang Huang
Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.
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