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公开(公告)号：US11108395B2
公开(公告)日：2021-08-31
申请号：US16822983
申请日：2020-03-18
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang
IPC: G01C11/00 , H03K19/00 , H03K17/16 , H03K19/0185 , H03K3/356 , H03K19/0944 , H03K17/687 , G11C5/02 , G11C11/16 , G11C7/06 , G11C7/10 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/16 , G05F3/26 , H02M3/07
Abstract: A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.
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公开(公告)号：US11436478B2
公开(公告)日：2022-09-06
申请号：US16874842
申请日：2020-05-15
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Cheng-Heng Chung , Ching-Yuan Lin
Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.
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公开(公告)号：US11170861B1
公开(公告)日：2021-11-09
申请号：US16939573
申请日：2020-07-27
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Hung-Yi Liao
Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a verification circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. Each of the plural multi-level memory cells is in one of X storage states. The current supply circuit provides plural reference currents. The path selecting circuit is connected with the current supply circuit and the n bit lines. The verification circuit is connected with the path selecting circuit, and generates n verification signals. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first verification device of the verification circuit is connected with the first path selector and generates a first verification signal.
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公开(公告)号：US10924112B2
公开(公告)日：2021-02-16
申请号：US16741791
申请日：2020-01-14
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang
IPC: G05F3/26 , H03K19/00 , H03K17/16 , H03K19/0185 , H03K3/356 , H03K19/0944 , H02M3/07 , H03K17/687 , G11C5/02 , G11C11/16 , G11C7/06 , G11C7/10 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/16
Abstract: A bandgap reference circuit is applied to the wide range supply voltage. When a power supply voltage is changed, the change amount of the bandgap voltage generated by the bandgap reference circuit is very low. The bandgap reference circuit includes a mirroring circuit, an input circuit and an operation amplifier. The mirroring circuit generates a first current, a second current and a third current to a first node, a second node and an output voltage of the bandgap reference circuit. The input circuit is connected with the first node to receive the first current and connected with the second node to receive the second current. A positive input terminal of the operation amplifier is connected with the first node. A negative input terminal of the operation amplifier is connected with the second node. An output terminal of the operation amplifier is connected with the mirroring circuit.
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公开(公告)号：US11837282B2
公开(公告)日：2023-12-05
申请号：US18047281
申请日：2022-10-18
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Sung-Ling Hsieh
CPC classification number: G11C11/5628 , G11C16/0408 , G11C16/10 , G11C16/3459 , H02M3/07 , G11C16/30
Abstract: A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.
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Patent Agency Ranking
公开(公告)号：US11521050B2
公开(公告)日：2022-12-06
申请号：US16874875
申请日：2020-05-15
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Cheng-Heng Chung , Ching-Yuan Lin
Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.
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公开(公告)号：US11508435B2
公开(公告)日：2022-11-22
申请号：US17379989
申请日：2021-07-19
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Sung-Ling Hsieh
Abstract: A charge pump apparatus including a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit is provided. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit controls the second charge pump system according to the output voltage to adjust the second boost voltage so that the output voltage approaches to a target output value.
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公开(公告)号：US20140211562A1
公开(公告)日：2014-07-31
申请号：US13755045
申请日：2013-01-31
Applicant: EMEMORY TECHNOLOGY INC.
Inventor： Che-Wei Chang , Chia-Fu Chang , Yu-Hsiung Tsai , Chia-Jung Hsu
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/30
Abstract: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.
Abstract translation: 闪速存储器包括编程电压发生器，多个存储器单元，限流器和多位程序控制单元。 程序电压发生器用于在检测周期期间提供恒定的编程电压，并在编程周期期间提供动态可调节的编程电压。 多个存储单元将多个漏极电流和多个数据线电压输出到多条数据线。 电流限制器用于接收参考电流和参考电压，从而控制多个漏极电流。 在检测周期期间，由多位程序控制单元检测具有最小电压电平的多条数据线电压的指定数据线电压。 在编程周期中，指定的数据线电压用作反馈电压，动态可调程序电压由编程电压发生器根据反馈电压产生。
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公开(公告)号：US20240161843A1
公开(公告)日：2024-05-16
申请号：US18370404
申请日：2023-09-20
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Chun-Hung Lin , Jen-Yu Peng , You-Ruei Chuang
Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.
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公开(公告)号：US11881274B2
公开(公告)日：2024-01-23
申请号：US17842835
申请日：2022-06-17
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Po-Ping Wang , Jen-Yu Peng
CPC classification number: G11C17/18 , G11C16/102 , G11C16/30 , G11C17/16
Abstract: A program control circuit for an antifuse-type one time programming memory cell array is provided. When the program action is performed, the program control circuit monitors the program current from the memory cell in real time and increases the program voltage at proper time. When the program control circuit judges that the program current generated by the memory cell is sufficient, the program control circuit confirms that the program action is completed.
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