公开(公告)号：US12255645B2

公开(公告)日：2025-03-18

申请号：US18227409

申请日：2023-07-28

Applicant: eMemory Technology Inc.

Inventor： Chia-Jung Hsu ,  Chun-Yuan Lo ,  Chun-Hsiao Li ,  Chang-Chun Lung

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  H03K19/0185

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

公开(公告)号：US20240395342A1

公开(公告)日：2024-11-28

申请号：US18417389

申请日：2024-01-19

Applicant: eMemory Technology Inc.

Inventor： Chia-Jung HSU ,  Yun-Jen Ting ,  Cheng-Heng Chung ,  Chun-Hsiao Li ,  Tsung-Mu Lai

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35 ,  H10B43/35

Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

公开(公告)号：US11049564B2

公开(公告)日：2021-06-29

申请号：US16803585

申请日：2020-02-27

Applicant: eMemory Technology Inc.

Inventor： Wein-Town Sun ,  Hsueh-Wei Chen ,  Chun-Hsiao Li ,  Wei-Ren Chen ,  Hong-Yi Liao

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/10

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

公开(公告)号：US20180019252A1

公开(公告)日：2018-01-18

申请号：US15648464

申请日：2017-07-13

Applicant: eMemory Technology Inc.

Inventor： Chun-Hsiao Li ,  Wei-Ren Chen ,  Wein-Town Sun

IPC: H01L29/788 ,  H01L29/36 ,  H01L23/528 ,  H01L29/08 ,  H01L21/326 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/11524 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/109 ,  G11C16/0433 ,  G11C16/12 ,  H01L21/326 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/0646 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7833 ,  H01L29/788 ,  H02M3/073 ,  H02M2001/007

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

公开(公告)号：US11316011B2

公开(公告)日：2022-04-26

申请号：US17095855

申请日：2020-11-12

Applicant: eMemory Technology Inc.

Inventor： Wein-Town Sun ,  Chun-Hsiao Li

IPC: G11C16/10 ,  H01L29/06 ,  H01L29/792 ,  G11C16/34 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11563 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11524 ,  H01L29/788

Abstract: An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate.

公开(公告)号：US20210111273A1

公开(公告)日：2021-04-15

申请号：US16853764

申请日：2020-04-21

Applicant: eMemory Technology Inc.

Inventor： Wein-Town Sun ,  Chun-Hsiao Li

IPC: H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L27/11524 ,  H01L27/11529

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

公开(公告)号：US09640262B2

公开(公告)日：2017-05-02

申请号：US14719342

申请日：2015-05-22

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu ,  Chun-Hsiao Li ,  Hsuen-Wei Chen

IPC: H01L29/788 ,  G11C16/08 ,  G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  H01L23/528 ,  H01L27/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/93 ,  H01L27/11524 ,  H03K3/356 ,  G11C17/14 ,  G11C29/00 ,  H01L23/525

CPC classification number: G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/11524 ,  H01L29/1079 ,  H01L29/4916 ,  H01L29/93 ,  H01L2924/0002 ,  H03K3/356182 ,  H01L2924/00

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

公开(公告)号：US11665895B2

公开(公告)日：2023-05-30

申请号：US17867678

申请日：2022-07-18

Applicant: eMemory Technology Inc.

Inventor： Wein-Town Sun ,  Chun-Hsiao Li

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/42 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7884 ,  H10B41/35 ,  H10B41/41

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

公开(公告)号：US20220352191A1

公开(公告)日：2022-11-03

申请号：US17867678

申请日：2022-07-18

Applicant: eMemory Technology Inc.

Inventor： Wein-Town Sun ,  Chun-Hsiao Li

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788

Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

公开(公告)号：US10115682B2

公开(公告)日：2018-10-30

申请号：US15481889

申请日：2017-04-07

Applicant: eMemory Technology Inc.

Inventor： Chun-Hsiao Li ,  Wei-Ren Chen ,  Hsueh-Wei Chen

IPC: H01L27/108 ,  H01L23/00 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11507 ,  H01L27/11529 ,  H01L29/423 ,  G06F7/58 ,  G11C17/16 ,  G11C17/18 ,  G11C16/04 ,  H01L27/11558 ,  H01L49/02 ,  H01L29/78

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.