公开(公告)号：US20160013199A1

公开(公告)日：2016-01-14

申请号：US14719342

申请日：2015-05-22

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu ,  Chun-Hsiao Li ,  Hsuen-Wei Chen

IPC: H01L27/115

CPC classification number: G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/11524 ,  H01L29/1079 ,  H01L29/4916 ,  H01L29/93 ,  H01L2924/0002 ,  H03K3/356182 ,  H01L2924/00

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

Abstract translation: 非易失性存储单元包括半导体衬底，第一OD区域，第二OD区域，将第一OD区域与第二OD区域分离的隔离区域，设置在第一OD区域上的PMOS选择晶体管和PMOS浮栅晶体管 串联连接到选择晶体管并且设置在第一OD区域上。 PMOS浮栅晶体管包括覆盖第一OD区的浮置栅极。 存储器P阱设置在半导体衬底中。 存储器N阱设置在存储器P中。 存储器P与第一OD区和第二OD区很好地重叠。 存储器P阱具有比隔离区域的沟槽深度更深的结深度。 存储器N阱具有比隔离区的沟槽深度浅的结深度。

公开(公告)号：US20210111180A1

公开(公告)日：2021-04-15

申请号：US17068836

申请日：2020-10-13

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu

IPC: H01L27/11531

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device.

公开(公告)号：US20150091074A1

公开(公告)日：2015-04-02

申请号：US14477818

申请日：2014-09-04

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu ,  Wei-Ren Chen ,  Hsuen-Wei Chen ,  Mu-Ying Tsao ,  Ying-Je Chen

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/11558 ,  G11C5/147 ,  G11C7/12 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/28 ,  G11C16/30 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/4916

Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.

Abstract translation: 非易失性存储器结构包括P衬底，P衬底中的N阱和PMOS存储晶体管。 PMOS存储晶体管包括浮动栅极和设置在靠近浮置栅极的辅助栅极。 浮置栅极和辅助栅极直接设置在PMOS存储晶体管的相同的浮置栅极沟道上。 在辅助栅极和浮置栅极之间提供间隙，使得辅助栅极和浮置栅极至少在浮动栅极通道的正上方彼此分离。

公开(公告)号：US08779520B2

公开(公告)日：2014-07-15

申请号：US13893794

申请日：2013-05-14

Applicant: eMemory Technology Inc.

Inventor： Wei-Ren Chen ,  Te-Hsun Hsu ,  Wen-Hao Lee

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L27/11517 ,  G11C16/10 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract translation: 一种可擦除可编程单一多晶硅非易失性存储器，包括：基板结构; 具有浮置栅极的浮栅晶体管，浮置栅极下方的栅氧化层和沟道区，其中沟道区形成在N阱区中; 以及擦除栅极区，其中浮置栅极延伸到擦除栅极区域并且与擦除栅极区域相邻，并且擦除栅极区域包括连接到擦除线电压和P阱区域的n型源极/漏极区域。 在衬底结构中形成N阱和P阱区。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US11569252B2

公开(公告)日：2023-01-31

申请号：US17068836

申请日：2020-10-13

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu

IPC: H01L27/115 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device.

公开(公告)号：US10192875B2

公开(公告)日：2019-01-29

申请号：US15297162

申请日：2016-10-19

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu

IPC: H01L29/788 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11519 ,  G11C16/10 ,  G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  G11C16/08

Abstract: A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed. The stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor  (1).

公开(公告)号：US20170040330A1

公开(公告)日：2017-02-09

申请号：US15297162

申请日：2016-10-19

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu

IPC: H01L27/115 ,  H01L29/10 ,  H01L29/788

CPC classification number: H01L27/11524 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/7881

Abstract: A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed. The stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor   (1)

公开(公告)号：US20150243669A1

公开(公告)日：2015-08-27

申请号：US14708297

申请日：2015-05-11

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825

Abstract: Provided is a memory device including a control gate, floating gates, an inter-gate insulating layer and a select gate. The control gate is disposed on a substrate. The floating gates are disposed between the control gate and the substrate, wherein a width of each floating gate is greater than a width of the control gate. The inter-gate insulating layer is disposed between the control gate and each of the floating gates. The select gate is disposed on the substrate adjacent to the control gate.

Abstract translation: 提供了一种包括控制栅极，浮置栅极，栅极间绝缘层和选择栅极的存储器件。 控制栅极设置在基板上。 浮置栅极设置在控制栅极和衬底之间，其中每个浮置栅极的宽度大于控制栅极的宽度。 栅极间绝缘层设置在控制栅极和每个浮置栅极之间。 选择栅极设置在与控制栅极相邻的衬底上。

公开(公告)号：US09099392B2

公开(公告)日：2015-08-04

申请号：US13941814

申请日：2013-07-15

Applicant: eMemory Technology Inc.

Inventor： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC: H01L21/28 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L21/28 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/401

Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

Abstract translation: 本发明提供一种制造可擦除可编程单多晶非易失性存储器的方法，包括以下步骤：在第一类型衬底中限定第一区域和第二区域; 在所述第一区域中形成第二类型井区域; 形成覆盖所述第一区域的表面的第一栅极氧化物层和第二栅极氧化物层，其中所述第二栅极氧化物层延伸到所述第二区域并邻近所述第二区域; 在第二区域中形成DDD区域; 在所述第二区域上方蚀刻所述第二栅极氧化物层的一部分; 形成覆盖所述第一和第二栅极氧化物层的两个多晶硅栅极; 以及限定所述DDD区域中的第二类型掺杂区域并限定所述第二类型阱区域中的第一类型掺杂区域。

公开(公告)号：US20140242763A1

公开(公告)日：2014-08-28

申请号：US14277064

申请日：2014-05-14

Applicant: eMemory Technology Inc.

Inventor： Wei-Ren Chen ,  Te-Hsun Hsu ,  Chih-Hsin Chen

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  G11C16/0425 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7881

Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.

Abstract translation: 非易失性存储器结构包括其上具有排列成一排的第一氧化物界限（OD）区域，第二OD区域和第三OD区域的半导体衬底。 第一，第二和第三OD区域通过隔离区域彼此分离。 隔离区域包括第一OD区域和第二OD区域之间的第一介入隔离区域和第二OD区域与第三OD区域之间的第二中间隔离区域。 在第一OD区上形成选择晶体管。 在第二OD区域上形成浮栅晶体管。 浮栅晶体管串联耦合到选择栅极晶体管。 浮栅晶体管包括与下面的第二OD区完全重叠并与第一和第二居间隔离区部分重叠的浮栅。