公开(公告)号：US20180342531A1

公开(公告)日：2018-11-29

申请号：US15607583

申请日：2017-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiromasa Susuki ,  Masanori Tsutsumi ,  Shigehisa Inoue ,  Junji Oh ,  Kensuke Yamaguchi ,  Seiji Shimabukuro ,  Yuji Fukano ,  Ryoichi Ehara ,  Youko Furihata

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

公开(公告)号：US10269620B2

公开(公告)日：2019-04-23

申请号：US15274451

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Sung Tae Lee ,  Yao-sheng Lee ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11548

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

公开(公告)号：US10014316B2

公开(公告)日：2018-07-03

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo Yu ,  Jayavel Pachamuthu ,  Jongsun Sel ,  Tuan Pham ,  Cheng-Chung Chu ,  Yao-Sheng Lee ,  Kensuke Yamaguchi ,  Masanori Terahara ,  Shuji Minagawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L21/336 ,  H01L29/167 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/78

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US10008570B2

公开(公告)日：2018-06-26

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Kento Kitamura ,  Tong Zhang ,  Chun Ge ,  Yanli Zhang ,  Satoshi Shimizu ,  Yasuo Kasagi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Johann Alsmeier ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US10916504B2

公开(公告)日：2021-02-09

申请号：US16441439

申请日：2019-06-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Mukae ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Raghuveer S. Makala ,  Yujin Terasawa

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.

公开(公告)号：US10249640B2

公开(公告)日：2019-04-02

申请号：US15176674

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Alexander Chu ,  Kensuke Yamaguchi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Yan LI ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

公开(公告)号：US10141331B1

公开(公告)日：2018-11-27

申请号：US15607583

申请日：2017-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiromasa Susuki ,  Masanori Tsutsumi ,  Shigehisa Inoue ,  Junji Oh ,  Kensuke Yamaguchi ,  Seiji Shimabukuro ,  Yuji Fukano ,  Ryoichi Ehara ,  Youko Furihata

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.

公开(公告)号：US12217965B2

公开(公告)日：2025-02-04

申请号：US17573429

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yujin Terasawa ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Masaaki Higashitani

IPC: H01L21/285 ,  C23C16/14 ,  C23C16/455 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20 ,  H10B63/00

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US12176203B2

公开(公告)日：2024-12-24

申请号：US17573452

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yujin Terasawa ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Masaaki Higashitani

IPC: H01L21/02 ,  C23C16/458

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.