公开(公告)号：US12150302B2

公开(公告)日：2024-11-19

申请号：US17679335

申请日：2022-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Senaka Kanakamedala ,  Raghuveer S. Makala ,  Peng Zhang ,  Yanli Zhang

IPC: H01L27/11582 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

公开(公告)号：US11972819B2

公开(公告)日：2024-04-30

申请号：US17872148

申请日：2022-07-25

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24

Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

公开(公告)号：US11805649B2

公开(公告)日：2023-10-31

申请号：US17385728

申请日：2021-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Srinivas Pulugurtha ,  Johann Alsmeier ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/762 ,  H01L29/10 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/1037 ,  H10B41/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

公开(公告)号：US11631686B2

公开(公告)日：2023-04-18

申请号：US17351720

申请日：2021-06-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Yanli Zhang ,  Jiahui Yuan ,  Raghuveer S. Makala ,  Senaka Kanakamedala

IPC: H01L29/49 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

公开(公告)号：US20220398439A1

公开(公告)日：2022-12-15

申请号：US17343240

申请日：2021-06-09

Applicant: SanDisk Technologies LLC

Inventor： Yanli Zhang

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L25/18 ,  G06N3/04 ,  G06N3/08 ,  G06F7/523

Abstract: A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

公开(公告)号：US11302716B2

公开(公告)日：2022-04-12

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Fei Zhou ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11585 ,  H01L23/528 ,  H01L23/522

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210408024A1

公开(公告)日：2021-12-30

申请号：US16916186

申请日：2020-06-30

Applicant: SanDisk Technologies LLC

Inventor： Sarath Puthenthermadam ,  Yanli Zhang ,  Huai-yuan Tseng ,  Peng Zhang

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L29/06 ,  H01L27/11582

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

公开(公告)号：US10985172B2

公开(公告)日：2021-04-20

申请号：US16251854

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Yanli Zhang ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US10916287B2

公开(公告)日：2021-02-09

申请号：US16454458

申请日：2019-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Johann Alsmeier

IPC: G11C11/22 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11592 ,  H01L27/11597 ,  H01L27/11585

Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.

公开(公告)号：US10811431B1

公开(公告)日：2020-10-20

申请号：US16457721

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang

IPC: H01L27/11597 ,  H01L27/11587 ,  G11C11/22 ,  G11C5/06

Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.