公开(公告)号：US10014316B2

公开(公告)日：2018-07-03

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo Yu ,  Jayavel Pachamuthu ,  Jongsun Sel ,  Tuan Pham ,  Cheng-Chung Chu ,  Yao-Sheng Lee ,  Kensuke Yamaguchi ,  Masanori Terahara ,  Shuji Minagawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L21/336 ,  H01L29/167 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/78

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US10403639B2

公开(公告)日：2019-09-03

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Orimoto ,  James Kai ,  Sayako Nagamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US09576967B1

公开(公告)日：2017-02-21

申请号：US15198175

申请日：2016-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hajime Kimura ,  Seiji Shimabukuro ,  Shuji Minagawa ,  Michiaki Sano ,  Masanori Tsutsumi

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively. The support pillar structures are formed with an outermost dielectric layer to prevent a leakage path to electrically conductive layers to be subsequently formed.

Abstract translation: 存储器开口和支撑开口通过半导体衬底上的绝缘层和隔离材料层的交替叠层形成。 通过在支撑开口下面的部分将半导体衬底的部分转换成掺杂杂质的半导体材料部分，可以防止在形成存储器开口中的外延沟道部分期间将半导体材料沉积在支撑开口中。 在从存储器开口内的半导体衬底的外延沟道部分的选择性生长期间，由于杂质掺杂半导体材料部分中的杂质种类，抑制了支撑开口中半导体材料的生长。 随后在外延通道部分和支撑开口中分别形成存储器堆叠结构和支撑柱结构。 支撑柱结构形成有最外面的电介质层，以防止随后形成导电层的泄漏路径。

公开(公告)号：US10347654B1

公开(公告)日：2019-07-09

申请号：US15977212

申请日：2018-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Shuji Minagawa ,  Hisakazu Otoi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11575

Abstract: Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. Memory opening fill structures are formed in the memory openings, and sacrificial backside opening fill structures are formed in the backside openings. Cavities are formed in volumes of the backside openings by removing the sacrificial backside opening fill structures. Remaining portions of the sacrificial material layers are replaced with material portions including electrically conductive layers. Each electrically conductive layer is formed as a continuous material layer including holes around the backside openings. Each electrically conductive layer is singulated into a plurality of electrically conductive strips by isotropically recessing the electrically conductive layers around each backside opening. Width-modulated cavities including expanded volumes of the backside openings are formed, and are filled with width-modulated insulating wall structures.

公开(公告)号：US20190027489A1

公开(公告)日：2019-01-24

申请号：US15818146

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi ORIMOTO ,  James KAI ,  Sayako Najamine ,  Takaaki Iwai ,  Shigeyuki Sugihara ,  Shuji Minagawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.