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1.再颁专利公开(公告)号：USRE46498E1
公开(公告)日：2017-08-01
申请号：US14230883
申请日：2014-03-31
Applicant: SanDisk Technologies Inc.
Inventor： Deepak Chandra Sekar , Nima Mokhlesi
CPC classification number: G11C5/146 , G11C16/10 , G11C16/26 , G11C2029/0409
Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.
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2.发明授权公开(公告)号：US09570185B2
公开(公告)日：2017-02-14
申请号：US14726301
申请日：2015-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459
Abstract: A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.
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3.再颁专利公开(公告)号：USRE46279E1
公开(公告)日：2017-01-17
申请号：US14290938
申请日：2014-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi
CPC classification number: G11C16/3418 , G11C11/5642 , G11C16/0483
Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.
Abstract translation: 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。
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公开(公告)号：US09047971B2
公开(公告)日：2015-06-02
申请号：US14290882
申请日：2014-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi , Mohan V. Dunga , Man Mui
IPC: G11C16/34 , G11C16/26 , G11C11/56 , G11C16/04 , H01L27/115
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11524
Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.
Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。 为了操作该系统，使用两条选择线，使得可以在块级别选择共享位线的NAND串（或存储器单元的其它分组）。 两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。 一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。
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5.发明授权Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution 有权基于存储单元阈值电压分布动态调整读取电压电平公开(公告)号：US09570184B2
公开(公告)日：2017-02-14
申请号：US14726207
申请日：2015-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459
Abstract: A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.
Abstract translation: 一种用于在一组非易失性存储器单元之间找到阈值电压分布的系统和方法，使得实施例可以将该分布信息合并到可改变用于读取存储器单元的读取比较电压的计算中，同时确保在读取电压之间的充分分离 可以读取存储器单元的不同数据状态。
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Patent Agency Ranking
公开(公告)号：US09076544B2
公开(公告)日：2015-07-07
申请号：US13674470
申请日：2012-11-12
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi , Mohan V. Dunga , Man Mui
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11524
Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.
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公开(公告)号：US20140269082A1
公开(公告)日：2014-09-18
申请号：US14290882
申请日：2014-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi , Mohan V. Dunga , Man Mui
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11524
Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.
Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。 为了操作该系统，使用两条选择线，使得可以在块级别选择共享位线的NAND串（或存储器单元的其它分组）。 两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。 一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。
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8.发明申请公开(公告)号：US20130246720A1
公开(公告)日：2013-09-19
申请号：US13888145
申请日：2013-05-06
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi , Henry Chin , Dengtao Zhao
IPC: G06F12/00
CPC classification number: G06F12/00 , G11C11/5642 , G11C16/04 , G11C16/28 , G11C29/00 , G11C29/02 , G11C29/028 , H03M13/11 , H03M13/37
Abstract: A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages.
Abstract translation: 提供了一组可靠性度量用于非易失性存储的迭代概率解码过程。 对被编程为多个编程状态的至少一组非易失性存储元件执行多个感测操作。 基于感测操作提供一组可靠性度量，例如对数似然比。 基于涉及至少一个非易失性存储元件的至少一个后续感测操作，可以通过迭代概率解码过程来使用该组可靠性度量来确定至少一个非易失性存储元件的编程状态。 可以在至少一组非易失性存储元件的不同年龄（例如，编程/擦除周期的数量）上执行多个感测操作，并且可靠性度量集合可以基于不同年龄段的平均值。
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公开(公告)号：US20160141301A1
公开(公告)日：2016-05-19
申请号：US14923824
申请日：2015-10-27
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi , Alexander Chu
CPC classification number: H01L27/11582 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3459 , H01L27/11517 , H01L27/11526 , H01L27/11573 , H01L27/11578
Abstract: A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.
Abstract translation: 三维堆叠的非易失性存储器件包括交替的电介质层和堆叠中的导电层，堆叠下方的多个位线以及堆叠之上的多个源极线。 每个位线都有一条独立的源线。 每个源极线连接到NAND串的不同子集。 每个位线连接到NAND串的不同子集。 同时验证多个数据状态。 对于数据状态，依次执行读取。 数据状态与被编程的存储器单元同时编程，以通过应用适当的源极线电压和位线电压来降低其编程速度变慢的数据状态。
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10.发明申请DYNAMIC ADJUSTMENT OF READ VOLTAGE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION 有权基于存储单元阈值电压分配的读取电压水平的动态调整公开(公告)号：US20150380096A1
公开(公告)日：2015-12-31
申请号：US14726301
申请日：2015-05-29
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Nima Mokhlesi
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C16/3459
Abstract: A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.
Abstract translation: 一种用于在一组非易失性存储器单元之间找到阈值电压分布的系统和方法，使得实施例可以将该分布信息合并到可改变用于读取存储器单元的读取比较电压的计算中，同时确保在读取电压之间的充分分离 可以读取存储器单元的不同数据状态。
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