公开(公告)号：US20150103595A1

公开(公告)日：2015-04-16

申请号：US14051416

申请日：2013-10-10

Applicant: Sandisk Technologies, Inc.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3454 ,  G11C7/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

Abstract: In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

Abstract translation: 在一块非易失性存储器中，位线电流随位线电压而增加。 对于电流感测存储器系统，在感测操作期间的平均位线电流仅需要超过某个阈值量以产生正确的结果。 对于在块中编程的第一个字线，与其连接的存储器单元在验证操作期间看到相对低的位线电阻。 在所公开的技术中，对具有较低验证位线电压的这些第一编程字线执行验证操作，以便减少多余的位线电流并节省功率。 在读取操作期间，该方案可以使连接到较低字线的存储单元的阈值电压更低。 为了补偿这种效果，公开了各种方案。

公开(公告)号：US09082502B2

公开(公告)日：2015-07-14

申请号：US14051416

申请日：2013-10-10

Applicant: SANDISK TECHNOLOGIES, INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/3454 ,  G11C7/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

Abstract: In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

Abstract translation: 在一块非易失性存储器中，位线电流随位线电压而增加。 对于电流感测存储器系统，在感测操作期间的平均位线电流仅需要超过某个阈值量以产生正确的结果。 对于在块中编程的第一个字线，与其连接的存储器单元在验证操作期间看到相对低的位线电阻。 在所公开的技术中，对具有较低验证位线电压的这些第一编程字线执行验证操作，以便减少多余的位线电流并节省功率。 在读取操作期间，该方案可以使连接到较低字线的存储单元的阈值电压更低。 为了补偿这种效果，公开了各种方案。

公开(公告)号：US09047971B2

公开(公告)日：2015-06-02

申请号：US14290882

申请日：2014-05-29

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Nima Mokhlesi ,  Mohan V. Dunga ,  Man Mui

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11524

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。 为了操作该系统，使用两条选择线，使得可以在块级别选择共享位线的NAND串（或存储器单元的其它分组）。 两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。 一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。

公开(公告)号：US09076544B2

公开(公告)日：2015-07-07

申请号：US13674470

申请日：2012-11-12

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Nima Mokhlesi ,  Mohan V. Dunga ,  Man Mui

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11524

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

公开(公告)号：US20140269082A1

公开(公告)日：2014-09-18

申请号：US14290882

申请日：2014-05-29

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Nima Mokhlesi ,  Mohan V. Dunga ,  Man Mui

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11524

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。 为了操作该系统，使用两条选择线，使得可以在块级别选择共享位线的NAND串（或存储器单元的其它分组）。 两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。 一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。

公开(公告)号：US20140254269A1

公开(公告)日：2014-09-11

申请号：US13793925

申请日：2013-03-11

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C29/025 ,  G11C29/028

Abstract: A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit lines reduces the space needed to implement the storage system. Each NAND string will have two drain side select gates. The non-volatile storage system will have two drain side selection lines each connected to one of the two drain side select gates so that the NAND strings sharing a bit line can be individually selected. To allow proper selection of a NAND string using the select gates, the select gates will be subjected to non-volatile programming in order to set the threshold voltage of the select gates to an appropriate level.

Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线并且共享公共位线的同一块中的NAND串（或其他存储器单元组）的对（或另一数量）。 通过共享位线，存储系统中需要较少的位线。 使用较少的位线减少了实现存储系统所需的空间。 每个NAND串将具有两个漏极侧选择栅极。 非易失性存储系统将具有两个漏极侧选择线，每条漏极侧选择线连接到两个漏极侧选择栅中的一个，使得可以单独选择共享位线的NAND串。 为了允许使用选择栅极适当地选择NAND串，选择栅极将经受非易失性编程，以便将选择栅极的阈值电压设置到适当的电平。

公开(公告)号：US09349452B2

公开(公告)日：2016-05-24

申请号：US13788183

申请日：2013-03-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/788 ,  G11C7/18 ,  G11C16/24 ,  H01L27/115

CPC classification number: G11C16/0425 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.

Abstract translation: 非易失性存储系统包括多组连接的非易失性存储元件。 每个组包括数据非易失性存储元件的公共侧上的多个连接的数据非易失性存储元件和多个选择栅极。 多个选择栅极包括第一选择栅极和第二选择栅极。 第一选择栅极具有用于组的第一子集的第一阈值电压和由于第二子集的有源区域注入导致第二阈值电压低于第二阈值电压的第二子集的第二阈值电压。 第一阈值电压。 每组的第二选择栅极具有可编程阈值电压。 多个位线中的每一个连接到多组连接的非易失性存储元件。

公开(公告)号：US09165656B2

公开(公告)日：2015-10-20

申请号：US13793925

申请日：2013-03-11

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C29/02

CPC classification number: G11C16/10 ,  G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C29/025 ,  G11C29/028

Abstract: A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit lines reduces the space needed to implement the storage system. Each NAND string will have two drain side select gates. The non-volatile storage system will have two drain side selection lines each connected to one of the two drain side select gates so that the NAND strings sharing a bit line can be individually selected. To allow proper selection of a NAND string using the select gates, the select gates will be subjected to non-volatile programming in order to set the threshold voltage of the select gates to an appropriate level.

Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线并且共享公共位线的同一块中的NAND串（或其他存储单元组）的对（或另一数量）。 通过共享位线，存储系统中需要较少的位线。 使用较少的位线减少了实现存储系统所需的空间。 每个NAND串将具有两个漏极侧选择栅极。 非易失性存储系统将具有两个漏极侧选择线，每条漏极侧选择线连接到两个漏极侧选择栅中的一个，使得可以单独选择共享位线的NAND串。 为了允许使用选择栅极适当地选择NAND串，选择栅极将经受非易失性编程，以便将选择栅极的阈值电压设置到适当的电平。

公开(公告)号：US20140254268A1

公开(公告)日：2014-09-11

申请号：US13788183

申请日：2013-03-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Mohan V. Dunga ,  Masaaki Higashitani

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/788

CPC classification number: G11C16/0425 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.

Abstract translation: 非易失性存储系统包括多组连接的非易失性存储元件。 每个组包括数据非易失性存储元件的公共侧上的多个连接的数据非易失性存储元件和多个选择栅极。 多个选择栅极包括第一选择栅极和第二选择栅极。 第一选择栅极具有用于组的第一子集的第一阈值电压和由于第二子集的有源区域注入导致第二阈值电压低于第二阈值电压的第二子集的第二阈值电压。 第一阈值电压。 每组的第二选择栅极具有可编程阈值电压。 多个位线中的每一个连接到多组连接的非易失性存储元件。

公开(公告)号：US20130128669A1

公开(公告)日：2013-05-23

申请号：US13674470

申请日：2012-11-12

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Nima Mokhlesi ,  Mohan V. Dunga ,  Man Mui

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427 ,  H01L27/11524

Abstract: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.

Abstract translation: 公开了一种非易失性存储系统，其包括连接到共享位线的同一块中的NAND串（或存储器单元的其它组）对。 为了操作该系统，使用两条选择线，使得可以在块级别选择共享位线的NAND串（或存储器单元的其它分组）。 两个选择线连接到共享位线的每个NAND串（或存储器单元的其它组）的选择门。 一组实施例通过将存储器单元的通道与所选择的字线的漏极侧的字线连接以偏置固定电位来避免读取操作期间的不希望的升压。