Pseudo block operation mode in 3D NAND
    4.
    发明授权
    Pseudo block operation mode in 3D NAND 有权
    3D NAND中的伪块操作模式

    公开(公告)号:US08913431B1

    公开(公告)日:2014-12-16

    申请号:US14274440

    申请日:2014-05-09

    Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

    Abstract translation: 一种3D NAND堆叠非易失性存储器件,包括:包括多个非易失性存储元件的串,所述串包括通道并垂直延伸穿过所述3D堆叠非易失性存储器件的层,并且所述多个存储元件 基于组分配被细分为不同的组,每组不同组包括多个存储元件中的多个相邻存储元件; 以及控制电路,与控制电路串联连接,以执行伪块操作模式。

    Techniques for programming of select gates in NAND memory
    9.
    发明授权
    Techniques for programming of select gates in NAND memory 有权
    NAND存储器中选择门的编程技术

    公开(公告)号:US09305648B2

    公开(公告)日:2016-04-05

    申请号:US14464122

    申请日:2014-08-20

    Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

    Abstract translation: 在根据NAND型架构形成的非易失性存储器中,在NAND串的一端或两端具有包括一些具有可编程阈值电压的多个选择栅极,该结构并且对应于这种选择栅极的有效编程。 在漏极侧,多个漏极选择晶体管的大部分可单独控制并用于偏置目的,而一个或多个其它漏极侧选择栅极被共同编程以设置其阈值电压。 独立地,在源极侧,多个源极选择晶体管的大部分结束是单独可控的并且用于偏置目的,而其他源极侧选择栅极被集体编程以设置调整其阈值电压。

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