公开(公告)号：US20240312494A1

公开(公告)日：2024-09-19

申请号：US18675997

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

公开(公告)号：US11869603B2

公开(公告)日：2024-01-09

申请号：US17401524

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  June Lee

IPC: G11C16/30 ,  G05F1/575 ,  G11C16/04

CPC classification number: G11C16/30 ,  G05F1/575 ,  G11C16/0483

Abstract: Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

公开(公告)号：US20220254418A1

公开(公告)日：2022-08-11

申请号：US17168970

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US20240371749A1

公开(公告)日：2024-11-07

申请号：US18777079

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Xiaojiang Guo ,  Naveen Kaushik ,  Shuai Xu ,  June Lee

IPC: H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

公开(公告)号：US20230317120A1

公开(公告)日：2023-10-05

申请号：US17426963

申请日：2020-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

公开(公告)号：US11763895B2

公开(公告)日：2023-09-19

申请号：US17873850

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

IPC: G11C16/04 ,  G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

CPC classification number: G11C16/30 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/0875 ,  G11C16/10 ,  G06F2212/603 ,  G11C16/0483

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US12068240B2

公开(公告)日：2024-08-20

申请号：US17461435

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Xiaojiang Guo ,  Naveen Kaushik ,  Shuai Xu ,  June Lee

IPC: H01L23/52 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5223 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

公开(公告)号：US12027227B2

公开(公告)日：2024-07-02

申请号：US17426963

申请日：2020-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

公开(公告)号：US20230046421A1

公开(公告)日：2023-02-16

申请号：US17401524

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  June Lee

IPC: G11C16/30 ,  G05F1/575

Abstract: Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

公开(公告)号：US20230017388A1

公开(公告)日：2023-01-19

申请号：US17873850

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Micheie Piccardi ,  Qing Liang

IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.