公开(公告)号：US20240312494A1

公开(公告)日：2024-09-19

申请号：US18675997

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

公开(公告)号：US11869603B2

公开(公告)日：2024-01-09

申请号：US17401524

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shuai Xu ,  Michele Piccardi ,  June Lee

IPC: G11C16/30 ,  G05F1/575 ,  G11C16/04

CPC classification number: G11C16/30 ,  G05F1/575 ,  G11C16/0483

Abstract: Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

公开(公告)号：US09613706B2

公开(公告)日：2017-04-04

申请号：US15059457

申请日：2016-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： June Lee ,  Fred Jaffin, III

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/20 ,  G11C16/34

CPC classification number: G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

Abstract: A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number of program/erase cycles has been previously applied to one or more memory cells of an array of memory cells of the memory device, using the counter to increment the number of program/erase cycles each time an additional program/erase cycle is applied to the one or more memory cells, using compare logic of the control logic to compare the incremented number of program/erase cycles to a numerical value, and using starting-voltage level control logic of the control logic to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the numerical value.

公开(公告)号：US20140153335A1

公开(公告)日：2014-06-05

申请号：US14063773

申请日：2013-10-25

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  June Lee ,  Chih Liang Chen

IPC: G11C16/10

CPC classification number: G11C7/1072 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C14/0009 ,  G11C16/10 ,  Y02D10/14

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract translation: 本公开包括用于操作存储器件的方法和电路。 用于操作存储器件的一个方法实施例包括通过至少部分地响应于第一接口触点上的写入使能信号向存储器件写入数据来控制通过异步模式的存储器接口的数据传输，以及从存储器件读取数据 至少部分地响应于第二接口触点上的读使能信号。 该方法还包括通过至少部分地响应于第一接口触点上的时钟信号传送数据，并且在不在异步模式下使用的接口触点上提供双向数据选通信号，来以同步模式控制数据传输。

公开(公告)号：US20230059543A1

公开(公告)日：2023-02-23

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

公开(公告)号：US20180366166A1

公开(公告)日：2018-12-20

申请号：US16110294

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  June Lee ,  Chih Liang Chen

IPC: G11C7/10 ,  G11C14/00 ,  G11C7/22 ,  G11C16/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C14/0009 ,  G11C16/10 ,  Y02D10/14

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

公开(公告)号：US09959931B2

公开(公告)日：2018-05-01

申请号：US15440430

申请日：2017-02-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： June Lee ,  Fred Jaffin, III

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/04

CPC classification number: G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

Abstract: A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during a first programming operation, comparing the determined number of program pulses required to program the sample of memory cells of the memory device to a target number of program pulses, and adjusting a program starting voltage level of one or more program pulses applied to one or more memory cells of the sample of memory cells during a second programming operation subsequent to the first programming operation when the determined number of program pulses required to program the sample of memory cells in the first programming operation is different than the target number so that the number of program pulses applied during the second programming operation tends toward the target number.

公开(公告)号：US10083725B2

公开(公告)日：2018-09-25

申请号：US15674586

申请日：2017-08-11

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  June Lee ,  Chih Liang Chen

IPC: G11C7/10 ,  G06F13/16 ,  G11C7/22 ,  G11C16/10 ,  G11C14/00

CPC classification number: G11C7/1072 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C14/0009 ,  G11C16/10 ,  Y02D10/14

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

公开(公告)号：US20160189782A1

公开(公告)日：2016-06-30

申请号：US15059457

申请日：2016-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： June Lee ,  Fred Jaffin, III

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/20

CPC classification number: G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

Abstract: A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number of program/erase cycles has been previously applied to one or more memory cells of an array of memory cells of the memory device, using the counter to increment the number of program/erase cycles each time an additional program/erase cycle is applied to the one or more memory cells, using compare logic of the control logic to compare the incremented number of program/erase cycles to a numerical value, and using starting-voltage level control logic of the control logic to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the numerical value.

Abstract translation: 一种方法包括将多个编程/擦除周期从存储器件的控制逻辑的存储器发送到控制逻辑的计数器，其中编程/擦除周期的数量已经预先应用于阵列的一个或多个存储器单元 的存储器单元的存储器单元，使用计数器在每次向一个或多个存储器单元施加附加的编程/擦除周期时增加编程/擦除周期的数量，使用控制逻辑的比较逻辑来比较递增的数 将编程/擦除周期转换为数值，并且使用控制逻辑的启动电压电平控制逻辑来基于递增的编程/擦除周期数的比较来调整程序启动电压电平和/或擦除起始电压电平 到数值。

公开(公告)号：US09299441B2

公开(公告)日：2016-03-29

申请号：US14220758

申请日：2014-03-20

Applicant: Micron Technology, Inc.

Inventor： June Lee ,  Fred Jaffin, III

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F11/10 ,  G11C11/56

CPC classification number: G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

Abstract: For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programed during the prior programming operation.

Abstract translation: 对于一个实施例，编程方法包括在编程操作期间对存储器件的一个或多个存储器单元进行编程，在存储器件内部确定编程所述存储器器件的一个或多个存储单元的样本所需的编程脉冲数 在编程操作期间调整存储器件，以及在随后的编程操作期间调整施加到所述一个或多个存储器单元的一个或多个编程脉冲的程序启动电压电平，至少部分地响应于编程所需的编程脉冲数 在先前的编程操作期间编程的一个或多个存储器单元的样本。