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公开(公告)号：US20240312494A1
公开(公告)日：2024-09-19
申请号：US18675997
申请日：2024-05-28
Applicant: Micron Technology, Inc.
Inventor： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC: G11C5/14
Abstract: In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.
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公开(公告)号：US12002526B2
公开(公告)日：2024-06-04
申请号：US17707766
申请日：2022-03-29
Applicant: Micron Technology, Inc.
Inventor： Pinchou Chiang , Arvind Muralidharan , James I. Esteves , Michele Piccardi , Theodore T. Pekny
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/10
Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.
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公开(公告)号：US12027227B2
公开(公告)日：2024-07-02
申请号：US17426963
申请日：2020-12-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC: G11C5/14
Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
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Patent Agency Ranking
4.发明申请公开(公告)号：US20210143732A1
公开(公告)日：2021-05-13
申请号：US17074510
申请日：2020-10-19
Applicant: Micron Technology, Inc.
Inventor： Arvind Muralidharan , Hari Giduturi
Abstract: Systems and methods of memory operation involving charge pump circuitry located on a die and coupled to external pump capacitors are disclosed. In one embodiment, an exemplary system may comprise a memory die containing a memory array and charge pump circuitry configured to generate a pump voltage supplied to the memory array, and one or more pump capacitors located external to the die and configured to hold stored charge that is used to generate the pump voltage. Some embodiments may include a tank capacitor, also located off-die, to condition the charge provided from the pump capacitor. According to further embodiments, the charge pump circuitry may include one or both of max current control circuitry and/or switch resistance control circuitry that may be utilized, for example, to adjust peak current.
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公开(公告)号：US20230317120A1
公开(公告)日：2023-10-05
申请号：US17426963
申请日：2020-12-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shuai Xu , Michele Piccardi , Arvind Muralidharan , June Lee , Qisong Lin , Scott A. Stoller , Jun Shen
IPC: G11C5/14
CPC classification number: G11C5/144
Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
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公开(公告)号：US20220223215A1
公开(公告)日：2022-07-14
申请号：US17707766
申请日：2022-03-29
Applicant: Micron Technology, Inc.
Inventor： Pinchou Chiang , Arvind Muralidharan , James I. Esteves , Michele Piccardi , Theodore T. Pekny
Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.
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公开(公告)号：US11315647B2
公开(公告)日：2022-04-26
申请号：US15929439
申请日：2020-05-01
Applicant: Micron Technology, Inc.
Inventor： Pinchou Chiang , Arvind Muralidharan , James I. Esteves , Michele Piccardi , Theodore T. Pekny
Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.
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公开(公告)号：US20210343351A1
公开(公告)日：2021-11-04
申请号：US15929439
申请日：2020-05-01
Applicant: Micron Technology, Inc.
Inventor： Pinchou Chiang , Arvind Muralidharan , James I. Esteves , Michele Piccardi , Theodore T. Pekny
Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.
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