公开(公告)号：US20170200793A1

公开(公告)日：2017-07-13

申请号：US15405111

申请日：2017-01-12

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32139 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7816

Abstract: A method for forming a steeped oxide on a substrate is described: successively forming a first pad oxide layer, a nitride layer, a second pad oxide layer and a poly layer on the substrate; etching the poly layer to have an opening for the stepped oxide region; isotropically etching the second pad oxide layer to the nitride layer through the opening to form a stepped trench; isotropically etching the nitride layer to the first pad oxide layer through the opening to expand the stepped trench; filling the stepped trench with dielectric material to form a dielectric layer; planarizing the dielectric layer; removing the poly layer; removing the second pad oxide layer; removing the nitride layer; removing the portion of the first pad oxide layer uncovered by the dielectric layer such that the remaining first pad oxide layer together the remaining dielectric layer forms the stepped oxide.

公开(公告)号：US20230261116A1

公开(公告)日：2023-08-17

申请号：US18170034

申请日：2023-02-16

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Daping Fu ,  Yanjie Lian

IPC: H01L29/808 ,  H01L27/085 ,  H01L21/8232

CPC classification number: H01L29/808 ,  H01L27/085 ,  H01L21/8232

Abstract: A semiconductor device includes a junction field effect transistor (JFET) device. The JFET device includes a substrate, a first well region, a first source region, a first drain region, a first gate region and a second gate region. A channel region is formed between the first source region and the first drain region along a first direction. The first gate region and the second gate region are located within the channel region, the first gate region includes a first surface extending from a top surface to a bottom surface of the first gate region, and the second gate region includes a second surface extending from a top surface to a bottom surface of the second gate region. The first surface is facing a second direction perpendicular to the first direction toward the second surface. A method of manufacturing such semiconductor device is also provided.

公开(公告)号：US10090200B2

公开(公告)日：2018-10-02

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082 ,  H01L29/732 ,  H01L29/06

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US12002848B2

公开(公告)日：2024-06-04

申请号：US17582159

申请日：2022-01-24

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816

Abstract: An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.

公开(公告)号：US20200185542A1

公开(公告)日：2020-06-11

申请号：US16709919

申请日：2019-12-10

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu

IPC: H01L29/872 ,  H01L29/06 ,  H01L21/761 ,  H01L29/66

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

公开(公告)号：US20240282808A1

公开(公告)日：2024-08-22

申请号：US18650680

申请日：2024-04-30

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816

Abstract: An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.

公开(公告)号：US20210020779A1

公开(公告)日：2021-01-21

申请号：US16922157

申请日：2020-07-07

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Ji-Hyoung Yoo

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

公开(公告)号：US20170186648A1

公开(公告)日：2017-06-29

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082

CPC classification number: H01L21/82285 ,  H01L21/761 ,  H01L27/0826 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/732

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US20220254876A1

公开(公告)日：2022-08-11

申请号：US17582159

申请日：2022-01-24

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.

公开(公告)号：US11205722B2

公开(公告)日：2021-12-21

申请号：US16922157

申请日：2020-07-07

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Ji-Hyoung Yoo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.