公开(公告)号：US20230261116A1

公开(公告)日：2023-08-17

申请号：US18170034

申请日：2023-02-16

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Daping Fu ,  Yanjie Lian

IPC: H01L29/808 ,  H01L27/085 ,  H01L21/8232

CPC classification number: H01L29/808 ,  H01L27/085 ,  H01L21/8232

Abstract: A semiconductor device includes a junction field effect transistor (JFET) device. The JFET device includes a substrate, a first well region, a first source region, a first drain region, a first gate region and a second gate region. A channel region is formed between the first source region and the first drain region along a first direction. The first gate region and the second gate region are located within the channel region, the first gate region includes a first surface extending from a top surface to a bottom surface of the first gate region, and the second gate region includes a second surface extending from a top surface to a bottom surface of the second gate region. The first surface is facing a second direction perpendicular to the first direction toward the second surface. A method of manufacturing such semiconductor device is also provided.

公开(公告)号：US10090200B2

公开(公告)日：2018-10-02

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082 ,  H01L29/732 ,  H01L29/06

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US20200185542A1

公开(公告)日：2020-06-11

申请号：US16709919

申请日：2019-12-10

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu

IPC: H01L29/872 ,  H01L29/06 ,  H01L21/761 ,  H01L29/66

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

公开(公告)号：US20170186648A1

公开(公告)日：2017-06-29

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082

CPC classification number: H01L21/82285 ,  H01L21/761 ,  H01L27/0826 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/732

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US09230956B2

公开(公告)日：2016-01-05

申请号：US14066626

申请日：2013-10-29

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Rongyao Ma ,  Tiesheng Li ,  Lei Zhang ,  Daping Fu

IPC: H01L27/06 ,  H01L27/146 ,  H01L27/098

CPC classification number: H01L27/0617 ,  H01L27/098 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/8083

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract translation: 具有第一掺杂型半导体衬底的JFET，位于半导体衬底上的第一掺杂型的外延层，位于外延层中的第二掺杂型的体区，位于第一掺杂类型的源区 外延层，位于体区的第二掺杂型的栅极区域和位于外延层中的第二掺杂型的屏蔽层，其中半导体衬底被配置为漏极区，屏蔽层为 形成在源极区域和漏极区域之间的导电路径。

公开(公告)号：US20140117416A1

公开(公告)日：2014-05-01

申请号：US14069293

申请日：2013-10-31

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Lei Zhang ,  Tiesheng Li ,  Rongyao Ma ,  Daping Fu

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/66893 ,  H01L21/8232 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7832 ,  H01L29/8083

Abstract: A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer.

Abstract translation: 具有在半导体层中形成的沟槽栅极MOSFET和垂直JFET的半导体器件。 在半导体器件中，垂直JFET的栅极区域可以电耦合到沟槽栅极MOSFET的源极区域，并且垂直JFET的漏极区域和沟槽栅极MOSFET的漏极区域可以共享公共区域 在半导体层。

公开(公告)号：US20210159330A1

公开(公告)日：2021-05-27

申请号：US16950447

申请日：2020-11-17

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Tao Hong ,  Daping Fu

IPC: H01L29/78 ,  H01L29/06

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

公开(公告)号：US20140117415A1

公开(公告)日：2014-05-01

申请号：US14066626

申请日：2013-10-29

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Rongyao Ma ,  Tiesheng Li ,  Lei Zhang ,  Daping Fu

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0617 ,  H01L27/098 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/8083

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract translation: 具有第一掺杂型半导体衬底的JFET，位于半导体衬底上的第一掺杂型的外延层，位于外延层中的第二掺杂型的体区，位于第一掺杂类型的源区 外延层，位于体区的第二掺杂型的栅极区域和位于外延层中的第二掺杂型的屏蔽层，其中半导体衬底被配置为漏极区，屏蔽层为 形成在源极区域和漏极区域之间的导电路径。

公开(公告)号：US11749751B2

公开(公告)日：2023-09-05

申请号：US16950447

申请日：2020-11-17

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Tao Hong ,  Daping Fu

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/782 ,  H01L29/0623 ,  H01L29/0653

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

公开(公告)号：US11081597B2

公开(公告)日：2021-08-03

申请号：US16709919

申请日：2019-12-10

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu

IPC: H01L29/872 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

Abstract: A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.