公开(公告)号：US10090200B2

公开(公告)日：2018-10-02

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082 ,  H01L29/732 ,  H01L29/06

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US20210020779A1

公开(公告)日：2021-01-21

申请号：US16922157

申请日：2020-07-07

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Ji-Hyoung Yoo

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

公开(公告)号：US20170186648A1

公开(公告)日：2017-06-29

申请号：US15384238

申请日：2016-12-19

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Daping Fu ,  Ji-Hyoung Yoo

IPC: H01L21/8228 ,  H01L29/10 ,  H01L29/08 ,  H01L21/761 ,  H01L27/082

CPC classification number: H01L21/82285 ,  H01L21/761 ,  H01L27/0826 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/732

Abstract: A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P− type first epitaxial layer formed on the buried layer, a P− type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

公开(公告)号：US11205722B2

公开(公告)日：2021-12-21

申请号：US16922157

申请日：2020-07-07

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Yanjie Lian ,  Ji-Hyoung Yoo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

Abstract: A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.