公开(公告)号：US10546840B2

公开(公告)日：2020-01-28

申请号：US15439817

申请日：2017-02-22

Applicant: VISHAY-SILICONIX

Inventor： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

公开(公告)号：US10546750B2

公开(公告)日：2020-01-28

申请号：US14988639

申请日：2016-01-05

Applicant: VISHAY-SILICONIX

Inventor： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/22 ,  H01L29/16 ,  H01L29/36 ,  H01L29/78

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

公开(公告)号：US10453953B2

公开(公告)日：2019-10-22

申请号：US15387378

申请日：2016-12-21

Applicant: Vishay-Siliconix

Inventor： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/49

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

公开(公告)号：US20180212048A1

公开(公告)日：2018-07-26

申请号：US15659539

申请日：2017-07-25

Applicant: Vishay-Siliconix

Inventor： Wenjie Zhang ,  Madhur Bobde ,  Qufei Chen ,  Kyle Terrill

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/781 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

公开(公告)号：US09978859B2

公开(公告)日：2018-05-22

申请号：US15614257

申请日：2017-06-05

Applicant: Vishay-Siliconix

Inventor： Chanho Park ,  Ayman Shibib ,  Kyle Terrill

IPC: H01L29/76 ,  H01L29/40 ,  H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/36 ,  H01L29/872

CPC classification number: H01L29/7802 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/872

Abstract: A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

公开(公告)号：US20170104096A1

公开(公告)日：2017-04-13

申请号：US15387378

申请日：2016-12-21

Applicant: Vishay-Siliconix

Inventor： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC: H01L29/78 ,  H01L21/321 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

公开(公告)号：US09443959B2

公开(公告)日：2016-09-13

申请号：US14711553

申请日：2015-05-13

Applicant: Vishay-Siliconix

Inventor： Kyle Terrill

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/74 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/66696 ,  H01L21/743 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7836

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

公开(公告)号：US20160218196A1

公开(公告)日：2016-07-28

申请号：US15093557

申请日：2016-04-07

Applicant: Vishay-Siliconix

Inventor： Wenjie Zhang ,  Madhur Bobde ,  Qufei Chen ,  Kyle Terrill

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/781 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

公开(公告)号：US20150194495A1

公开(公告)日：2015-07-09

申请号：US14663872

申请日：2015-03-20

Applicant: Vishay-Siliconix

Inventor： Misbah Ul Azam ,  Kyle Terrill

IPC: H01L29/40 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/76237 ,  H01L29/0615 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7813

Abstract: A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench.

Abstract translation: 在一个实施例中，一种方法可以包括在衬底中形成芯沟槽和终端沟槽。 端接沟槽比芯沟宽。 此外，可以沉积填充芯沟槽并对端接沟槽的侧壁和底部进行排列的第一氧化物。 可以将第一多晶硅沉积到端接沟槽中。 可以在第一多晶硅上沉积第二氧化物。 掩模可以沉积在第二氧化物和端接沟槽之上。 可以从芯沟槽去除第一氧化物。 可以沉积第三氧化物，其沿着芯沟槽的侧壁和底部排列。 端接沟槽内的第一氧化物比芯沟内的第三氧化物厚。

公开(公告)号：US09064896B2

公开(公告)日：2015-06-23

申请号：US14102208

申请日：2013-12-10

Applicant: Vishay-Siliconix

Inventor： Kyle Terrill

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/74 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/66696 ,  H01L21/743 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7836

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract translation: LDMOS（横向扩散金属氧化物半导体）结构将源极连接到衬底以及栅极屏蔽，同时利用这种接触的减小的面积。 该结构包括导电基底层，源极和漏极接触; 漏极接触件通过至少一个中间层与基底层分离。 导电沟槽状馈通元件穿过中间层并接触衬底和源极以电连接漏极接触和衬底层。