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公开(公告)号：US20250127068A1
公开(公告)日：2025-04-17
申请号：US18485209
申请日：2023-10-11
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Mingche Wu , Ning Ge
Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode comprising ruthenium, and a switching oxide layer fabricated between the first electrode and the second electrode. The first electrode includes at least one of palladium, titanium nitride, or tantalum nitride. The switching oxide layer comprises at least one transition metal oxide. In some embodiments, the RRAM device further includes an interface layer positioned between the switching oxide layer and the second electrode and/or an interface layer positioned between the first electrode and the switching oxide layer.
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2.发明申请公开(公告)号：US20250031587A1
公开(公告)日：2025-01-23
申请号：US18909276
申请日：2024-10-08
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.
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3.发明授权公开(公告)号：US12127487B2
公开(公告)日：2024-10-22
申请号：US18058337
申请日：2022-11-23
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
CPC classification number: H10N70/826 , H10B63/80 , H10N70/841 , H10N70/8833
Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.
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公开(公告)号：US11985911B2
公开(公告)日：2024-05-14
申请号：US17651790
申请日：2022-02-19
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
CPC classification number: H10N70/841 , H10B63/80 , H10N70/023 , H10N70/8833
Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.
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公开(公告)号：US20250098556A1
公开(公告)日：2025-03-20
申请号：US18899076
申请日：2024-09-27
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
Abstract: A method for forming a crossbar circuit is provided. The method may include forming a Resistive Random-Access Memory (RRAM) stack on a first line electrode and a substrate, forming an isolation layer on the first line electrode and the RRAM stack, etching the isolation layer to expose a top surface of the RRAM stack, and forming a selector stack on the top surface of the RRAM stack, a sidewall of the isolation layer, and an upper surface of the isolation layer. The method may further include forming a second line electrode on the selector stack.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240276895A1
公开(公告)日：2024-08-15
申请号：US18646738
申请日：2024-04-25
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
CPC classification number: H10N70/841 , H10B63/80 , H10N70/023 , H10N70/8833
Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.
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公开(公告)号：US20240099023A1
公开(公告)日：2024-03-21
申请号：US18052071
申请日：2022-11-02
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
Abstract: The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.
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8.发明授权公开(公告)号：US11283018B2
公开(公告)日：2022-03-22
申请号：US16367184
申请日：2019-03-27
Applicant: TETRAMEM INC.
Inventor： Ning Ge , Minxian Zhang
Abstract: Technologies relating to RRAM-based crossbar array circuits with increase temperature stability are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the filament includes nitrogen-doped Ta2O5, Ta2N/Ta2O5, or TaNyOz.
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公开(公告)号：US11217630B2
公开(公告)日：2022-01-04
申请号：US16393883
申请日：2019-04-24
Applicant: TETRAMEM INC.
Inventor： Minxian Zhang , Ning Ge
Abstract: Technologies relating to implementing memristor crossbar arrays using non-filamentary RRAM cells are disclosed. In some implementations, an apparatus comprises: a first row wire; a first column wire; a non-filamentary RRAM; and an access control device. The non-filamentary RRAM and the access control device are serially connected; the non-filamentary RRAM and the access control device connect the first row wire with the first column wire. The non-filamentary RRAM and the access control device may form a cross-point device. The cross-point device may be less than 40×40 nm2. A set current of the non-filamentary RRAM may be no more than 10 μA; and a reset current of the non-filamentary RRAM is no more than 10 μA. The access control device may comprise a transistor or a selector.
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公开(公告)号：US11177438B2
公开(公告)日：2021-11-16
申请号：US16421166
申请日：2019-05-23
Applicant: TETRAMEM INC.
Inventor： Minxian Zhang , Ning Ge
Abstract: An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.
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