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公开(公告)号：US20250127068A1
公开(公告)日：2025-04-17
申请号：US18485209
申请日：2023-10-11
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Mingche Wu , Ning Ge
Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode comprising ruthenium, and a switching oxide layer fabricated between the first electrode and the second electrode. The first electrode includes at least one of palladium, titanium nitride, or tantalum nitride. The switching oxide layer comprises at least one transition metal oxide. In some embodiments, the RRAM device further includes an interface layer positioned between the switching oxide layer and the second electrode and/or an interface layer positioned between the first electrode and the switching oxide layer.
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2.发明申请公开(公告)号：US20250031587A1
公开(公告)日：2025-01-23
申请号：US18909276
申请日：2024-10-08
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.
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公开(公告)号：US12198761B2
公开(公告)日：2025-01-14
申请号：US18060420
申请日：2022-11-30
Applicant: TetraMem Inc.
Inventor： Ning Ge
Abstract: The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.
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4.发明授权公开(公告)号：US12127487B2
公开(公告)日：2024-10-22
申请号：US18058337
申请日：2022-11-23
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
CPC classification number: H10N70/826 , H10B63/80 , H10N70/841 , H10N70/8833
Abstract: The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.
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公开(公告)号：US11985911B2
公开(公告)日：2024-05-14
申请号：US17651790
申请日：2022-02-19
Applicant: TetraMem Inc.
Inventor： Minxian Zhang , Ning Ge
CPC classification number: H10N70/841 , H10B63/80 , H10N70/023 , H10N70/8833
Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.
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Patent Agency Ranking
公开(公告)号：US20240137038A1
公开(公告)日：2024-04-25
申请号：US18156171
申请日：2023-01-18
Applicant: TetraMem Inc.
Inventor： Ning Ge , Hengfang Zhu , Sangsoo Lee , Wenbo Yin
IPC: H03M1/36
CPC classification number: H03M1/365
Abstract: The present disclosure provides a voltage divider circuit utilizing non-volatile memory devices. The non-volatile memory device may include, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc. The voltage divider circuit may include one or more first non-volatile memory devices that form a resistor ladder. The resistor ladder may produce a plurality of reference voltages when the resistor ladder is connected between two voltages.
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公开(公告)号：US20230102234A1
公开(公告)日：2023-03-30
申请号：US18060420
申请日：2022-11-30
Applicant: TetraMem Inc.
Inventor： Ning Ge
Abstract: The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.
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公开(公告)号：US20230088575A1
公开(公告)日：2023-03-23
申请号：US18052700
申请日：2022-11-04
Applicant: TetraMem Inc.
Inventor： Ning Ge
Abstract: Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.
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公开(公告)号：US11610942B2
公开(公告)日：2023-03-21
申请号：US17357341
申请日：2021-06-24
Applicant: TetraMem Inc.
Inventor： Ning Ge
Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.
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公开(公告)号：US11539906B2
公开(公告)日：2022-12-27
申请号：US16702444
申请日：2019-12-03
Applicant: TETRAMEM INC.
IPC: H04N5/3745 , G11C13/00 , H04N5/378
Abstract: Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.
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