公开(公告)号：US11232983B2

公开(公告)日：2022-01-25

申请号：US17011823

申请日：2020-09-03

Applicant: Tessera, Inc.

Inventor： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga K. Shobha

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20220115269A1

公开(公告)日：2022-04-14

申请号：US17556382

申请日：2021-12-20

Applicant: Tessera, Inc.

Inventor： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga Shobha

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US10593591B2

公开(公告)日：2020-03-17

申请号：US16118998

申请日：2018-08-31

Applicant: TESSERA, INC.

Inventor： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga K. Shobha

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20210043563A1

公开(公告)日：2021-02-11

申请号：US17068230

申请日：2020-10-12

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Takeshi Nogami ,  Raghuveer R. Patlolla

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

公开(公告)号：US10770347B2

公开(公告)日：2020-09-08

申请号：US16657169

申请日：2019-10-18

Applicant: TESSERA, INC.

Inventor： Daniel C. Edelstein ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga K. Shobha

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US10804193B2

公开(公告)日：2020-10-13

申请号：US15609672

申请日：2017-05-31

Applicant: TESSERA, INC.

Inventor： Benjamin D. Briggs ,  Takeshi Nogami ,  Raghuveer R. Patlolla

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

公开(公告)号：US10763166B2

公开(公告)日：2020-09-01

申请号：US16250561

申请日：2019-01-17

Applicant: TESSERA, INC.

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Takeshi Nogami ,  Christopher J. Penny

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/3115 ,  H01L23/532 ,  H01L23/522

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.