公开(公告)号：US20200328156A1

公开(公告)日：2020-10-15

申请号：US16888245

申请日：2020-05-29

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala ,  David L. Rath ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

公开(公告)号：US10763166B2

公开(公告)日：2020-09-01

申请号：US16250561

申请日：2019-01-17

Applicant: TESSERA, INC.

Inventor： Benjamin D. Briggs ,  Elbert Huang ,  Takeshi Nogami ,  Christopher J. Penny

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/3115 ,  H01L23/532 ,  H01L23/522

Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

公开(公告)号：US20220181205A1

公开(公告)日：2022-06-09

申请号：US17571814

申请日：2022-01-10

Applicant: Tessera, Inc.

Inventor： Benjamin D. Briggs ,  Jessica Dechene ,  Elbert Huang ,  Joe Lee ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.