公开(公告)号：US10659214B2

公开(公告)日：2020-05-19

申请号：US15695491

申请日：2017-09-05

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta ,  Sanket Naik ,  Jayesh Wadekar

IPC: H04L7/00 ,  H04L7/033 ,  H04L7/06 ,  H04L7/04 ,  H04L27/26

Abstract: A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

公开(公告)号：US10749531B1

公开(公告)日：2020-08-18

申请号：US16673835

申请日：2019-11-04

Applicant: Synopsys, Inc.

Inventor： Sanket Naik ,  Akarsh Joshi ,  Gopal Krishna Ullal Nayak

IPC: H03K23/66 ,  H03K23/68 ,  H03K21/02 ,  H03K21/10 ,  H03L7/197

Abstract: A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

公开(公告)号：US10320389B2

公开(公告)日：2019-06-11

申请号：US15876693

申请日：2018-01-22

Applicant: Synopsys, Inc.

Inventor： Vijay A. Nebhrajani ,  Sanket Naik

IPC: H03K19/177 ,  G01R31/3185 ,  G11C16/02

Abstract: Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

公开(公告)号：US10073799B1

公开(公告)日：2018-09-11

申请号：US15876752

申请日：2018-01-22

Applicant: Synopsys, Inc.

Inventor： Vijay A. Nebhrajani ,  Sanket Naik

IPC: G06F13/40 ,  G05B19/045

CPC classification number: G06F13/4018 ,  G05B19/045 ,  G05B2219/23289

Abstract: The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the present disclosure can include a control Finite State Machine (FSM) that is configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. The pDWC can be configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1≤m≤M and 1≤n≤N.