公开(公告)号：US10659214B2

公开(公告)日：2020-05-19

申请号：US15695491

申请日：2017-09-05

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta ,  Sanket Naik ,  Jayesh Wadekar

IPC: H04L7/00 ,  H04L7/033 ,  H04L7/06 ,  H04L7/04 ,  H04L27/26

Abstract: A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

公开(公告)号：US10516523B2

公开(公告)日：2019-12-24

申请号：US16169454

申请日：2018-10-24

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta

IPC: H04L7/06 ,  H04L12/863 ,  H03M9/00 ,  H04J3/04 ,  H04J3/06

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

公开(公告)号：US20190089359A1

公开(公告)日：2019-03-21

申请号：US15863422

申请日：2018-01-05

Applicant: Synopsys, Inc.

Inventor： Ravi Mehta ,  Manjunath Shet SN ,  Biman Chattopadhyay ,  Vishal Dilipbhai Nimbark

IPC: H03L7/08 ,  H04L7/04

Abstract: A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.

公开(公告)号：US20200084016A1

公开(公告)日：2020-03-12

申请号：US16686030

申请日：2019-11-15

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta

IPC: H04L7/06 ,  H04J3/06 ,  H04J3/04 ,  H03M9/00 ,  H04L12/863

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

公开(公告)号：US20190181868A1

公开(公告)日：2019-06-13

申请号：US15901212

申请日：2018-02-21

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Jairaj Naik K R

IPC: H03L7/08 ,  H03L7/089 ,  H04L7/00

CPC classification number: H03L7/0802 ,  H03L7/0807 ,  H03L7/0895 ,  H04L7/0008

Abstract: A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

公开(公告)号：US10236843B2

公开(公告)日：2019-03-19

申请号：US15862510

申请日：2018-01-04

Applicant: Synopsys, Inc.

Inventor： Jayesh Wadekar ,  Ravi Mehta ,  Biman Chattopadhyay

IPC: H03F3/45 ,  H03F3/72

Abstract: A high gain differential amplifier includes first through eighth transistors, first through third degeneration resistors, and first through third current sources. The fourth and fifth transistors form a p-type metal-oxide-semiconductor (PMOS) transistor pair. Further, the second and eighth transistors form a current mirror circuit. The PMOS transistor pair and the current mirror circuit form a common mode feedback circuit. The high gain differential amplifier controls the common-mode output voltage with the common mode feedback circuit and a reference voltage.

公开(公告)号：US10205445B1

公开(公告)日：2019-02-12

申请号：US15862559

申请日：2018-01-04

Applicant: Synopsys, Inc.

Inventor： Shourya Kansal ,  Biman Chattopadhyay ,  Ravi Mehta ,  Jayesh Wadekar

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03F3/45

Abstract: A duty cycle correction (DCC) circuit includes first and second pluralities of logic gates, a low pass filter, an error amplifier, and a differential amplifier. The DCC circuit receives first and second clock signals from the VCO. The first and second pluralities of logic gates receive first and second superimposed clock signals and generate first and second output clock signals, respectively. The error amplifier rectifies a common error of the first and second output clock signals, and generates a common mode error voltage signal. The differential amplifier generates first and second error signals based on the common mode error voltage signal. The first and second error signals converge the duty cycles of the first and second output clock signals to a 50% duty cycle.

公开(公告)号：US10142097B2

公开(公告)日：2018-11-27

申请号：US15349193

申请日：2016-11-11

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta

IPC: H04L7/06 ,  H04L12/863 ,  H03M9/00 ,  H04J3/04 ,  H04J3/06

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

公开(公告)号：US11223469B2

公开(公告)日：2022-01-11

申请号：US16686030

申请日：2019-11-15

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay ,  Ravi Mehta

IPC: H04L7/06 ,  H04L12/863 ,  H03M9/00 ,  H04J3/04 ,  H04J3/06

Abstract: A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

公开(公告)号：US10972105B1

公开(公告)日：2021-04-06

申请号：US16718830

申请日：2019-12-18

Applicant: Synopsys, Inc.

Inventor： Biman Chattopadhyay

IPC: H03L7/07 ,  G06F1/08 ,  H03L7/197 ,  H03L7/08

Abstract: A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.