公开(公告)号：US12113494B2

公开(公告)日：2024-10-08

申请号：US17836709

申请日：2022-06-09

Applicant: Socionext Inc.

Inventor： Takuya Fujimura ,  Hideki Kano

IPC: H03F3/45 ,  H04L25/03

CPC classification number: H03F3/45179 ,  H03F3/45636 ,  H04L25/03146 ,  H03F2200/453

Abstract: In a differential amplifier circuit, a differential amplifier circuit unit includes: first and second transistors provided between a current source circuit and a load circuit, which receives differential input signals at gates to generate differential output signals at drains; and a third transistor connected between sources of the first and second transistors, which receives a control signal at a gate. A replica amplifier circuit unit includes: a voltage generation circuit which generates first and second reference voltages; first and second replica transistors which receives the first and second reference voltages at gates to generate replica output signals at drains; a third replica transistor connected between sources of the first and second replica transistors, which receives the control signal at a gate; and an operational amplifier which generates the control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.

公开(公告)号：US12081219B2

公开(公告)日：2024-09-03

申请号：US18318303

申请日：2023-05-16

Applicant: Socionext Inc.

Inventor： Takuya Fujimura

IPC: H03K5/13 ,  H03D7/00 ,  H04L25/03

CPC classification number: H03K5/13 ,  H03D7/00 ,  H04L25/03057

Abstract: A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.