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Patent Agency Ranking
公开(公告)号：US11251800B2
公开(公告)日：2022-02-15
申请号：US17098071
申请日：2020-11-13
Applicant: SOCIONEXT INC.
Inventor： Hideki Kano , Tatsuya Sakae
Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.
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公开(公告)号：US20210067165A1
公开(公告)日：2021-03-04
申请号：US17098071
申请日：2020-11-13
Applicant: Socionext Inc.
Inventor： Hideki Kano , Tatsuya Sakae
Abstract: A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.
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公开(公告)号：US12113494B2
公开(公告)日：2024-10-08
申请号：US17836709
申请日：2022-06-09
Applicant: Socionext Inc.
Inventor： Takuya Fujimura , Hideki Kano
CPC classification number: H03F3/45179 , H03F3/45636 , H04L25/03146 , H03F2200/453
Abstract: In a differential amplifier circuit, a differential amplifier circuit unit includes: first and second transistors provided between a current source circuit and a load circuit, which receives differential input signals at gates to generate differential output signals at drains; and a third transistor connected between sources of the first and second transistors, which receives a control signal at a gate. A replica amplifier circuit unit includes: a voltage generation circuit which generates first and second reference voltages; first and second replica transistors which receives the first and second reference voltages at gates to generate replica output signals at drains; a third replica transistor connected between sources of the first and second replica transistors, which receives the control signal at a gate; and an operational amplifier which generates the control signal according to a difference between at least one of the first and second reference voltages and the replica output signal.
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公开(公告)号：US11901868B2
公开(公告)日：2024-02-13
申请号：US16986931
申请日：2020-08-06
Applicant: SOCIONEXT INC.
Inventor： Hideki Kano
CPC classification number: H03F3/45179 , H04L25/4917 , G06F7/50
Abstract: There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.
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公开(公告)号：US11271568B2
公开(公告)日：2022-03-08
申请号：US17118331
申请日：2020-12-10
Applicant: SOCIONEXT INC.
Inventor： Hideki Kano
IPC: H03K23/00 , H03K19/17736 , H03K19/096 , H03K21/02 , H03K21/10 , H03K23/58 , H03K23/60
Abstract: A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.
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