公开(公告)号：US10923498B2

公开(公告)日：2021-02-16

申请号：US16394233

申请日：2019-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Satoshi Shimizu ,  Makoto Koto

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

公开(公告)号：US10943917B2

公开(公告)日：2021-03-09

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Makoto Koto ,  Sayako Nagamine ,  Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L21/762 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.