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    THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF
    5.
    发明申请
    THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF 有权
    具有BIRDS包含浮动门的三维NAND器件及其制造方法

    公开(公告)号：US20150008505A1

    公开(公告)日：2015-01-08

    申请号：US14183152

    申请日：2014-02-18

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Henry Chien ,  Donovan Lee ,  Vinod R. Purayath ,  Yuan Zhang ,  James K. Kai ,  George Matamis

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

    Abstract translation: 一种制造单片三维NAND串的方法，包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括电绝缘材料，第二材料包括半导体或导体材料。 该方法还包括蚀刻堆叠以在堆叠中形成前侧开口，在暴露在前侧开口中的第一材料和第二材料的交替层的堆叠层之上形成阻挡电介质层，形成半导体或金属电荷存储 在所述阻挡电介质上方形成在所述电荷存储层上方的隧道介电层，在所述隧道介电层上形成半导体沟道层，蚀刻所述堆叠以在所述堆叠中形成背侧开口，去除所述第一材料的至少一部分 层和介电层的部分。

    Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices
    6.
    发明申请
    Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices 有权
    用于非易失性存储器件的纳米增强型混合浮动栅极

    公开(公告)号：US20140252447A1

    公开(公告)日：2014-09-11

    申请号：US13792662

    申请日：2013-03-11

    Applicant: SANDISK TECHNOLOGIES, INC.

    Inventor： Donovan Lee ,  James K. Kai ,  George Samachisa ,  Henry Chien ,  George Matamis ,  Vinod R. Purayath

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/66825 ,  B82Y40/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887

    Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

    Abstract translation: 存储器件和制造存储器件的方法，该存储器件包括半导体沟道，位于半导体沟道上方的隧道介电层，位于隧道介电层上方的浮动栅极，该浮栅包括导电材料的连续层， 导电材料的至少一个突出物，面向隧道介电层并电连接到连续层，位于浮动栅极上方的阻挡电介质区域和位于阻挡电介质层上方的控制栅极。

    Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory
    7.
    发明申请
    Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory 有权
    金属控制门结构和非易失性存储器中的空气间隙隔离

    公开(公告)号：US20130334587A1

    公开(公告)日：2013-12-19

    申请号：US13947530

    申请日：2013-07-22

    Applicant: SanDisk Technologies Inc.

    Inventor： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

    IPC: H01L27/115

    CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

    Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

    Abstract translation: 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

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