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公开(公告)号：US10714187B2
公开(公告)日：2020-07-14
申请号：US16679476
申请日：2019-11-11
Applicant: RAYMX Microelectronics Corp.
Inventor： Yi-Lin Hsieh , Jing-Long Xiao , Cheng-Yu Chen , Wang-Sheng Lin
Abstract: A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.
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公开(公告)号：US10594366B2
公开(公告)日：2020-03-17
申请号：US16367393
申请日：2019-03-28
Applicant: RayMX Microelectronics, Corp.
Inventor： Jo-Hua Wu , Cheng-Yu Chen
Abstract: A data storage device includes a power line communication (PLC) circuit and a storage controller. The PLC circuit is coupled to a power line. The storage controller is coupled to the PLC circuit. The storage controller is configured to access a plurality of memory block. The PLC circuit is configured to carry at least one signal outputted from the storage controller on the power line, in order to transmit the at least one signal to an external device such that an operational state of the data storage device can be debugged/monitored.
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公开(公告)号：US20200075107A1
公开(公告)日：2020-03-05
申请号：US16244321
申请日：2019-01-10
Applicant: RayMx Microelectronics, Corp
Inventor： Shih-Fu Huang , Shu-Min Lin , Jo-Hua Wu , Cheng-Yu Chen
Abstract: A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.
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公开(公告)号：US10852991B1
公开(公告)日：2020-12-01
申请号：US16548934
申请日：2019-08-23
Applicant: RAYMX Microelectronics Corp.
Inventor： Min-Yan Ciou , Cheng-Yu Chen
IPC: G06F3/06
Abstract: A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.
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公开(公告)号：US10776288B2
公开(公告)日：2020-09-15
申请号：US16537692
申请日：2019-08-12
Applicant: RayMX Microelectronics, Corp.
Inventor： Cheng-Yu Chen , Chih-Ching Chien
Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple types of interface according to a determined result; wherein the memory control device operates in the adapted operation mode to receive at least one access command from the host to access the memory module.
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Patent Agency Ranking
公开(公告)号：US11449310B2
公开(公告)日：2022-09-20
申请号：US16546459
申请日：2019-08-21
Applicant: RAYMX Microelectronics Corp.
Inventor： Shih-Fu Huang , Cheng-Yu Chen , Yi-Lin Hsieh , Jing-Long Xiao
Abstract: A method for generating a random number, applied in a random number generator coupled to a flash memory is disclosed. the method comprises: selecting a plurality of cells from the flash memory; initializing the selecting cells of the flash memory; programming the selecting cells to obtain a plurality of first potential values of the selecting cells; re-initializing the selecting cells of the flash memory; re-programming the selecting cells to obtain a plurality of second potential values of the selecting cells; and processing the first potential values and the second potential values according to a predetermined algorithm to generating the random number.
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公开(公告)号：US10956087B2
公开(公告)日：2021-03-23
申请号：US16405195
申请日：2019-05-07
Applicant: RAYMX Microelectronics Corp.
Inventor： Shih-Fu Huang , Cheng-Yu Chen
IPC: G06F3/06
Abstract: A memory controller includes: an interface configured to operably communicate with a host device; a temperature detecting circuit configured to operably detect an ambient temperature, wherein when the ambient temperature is beyond a predetermined temperature range, the temperature detecting circuit generates a control signal; and a processing circuit coupled to the interface and the temperature detecting circuit, for selecting one of a plurality of data program schemes to program data into a first storage block of a flash memory according to the control signal.
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公开(公告)号：US10776011B2
公开(公告)日：2020-09-15
申请号：US16293770
申请日：2019-03-06
Applicant: RayMX Microelectronics, Corp.
Inventor： Cheng-Yu Chen , Chih-Ching Chien , Yen-Chung Chen
Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.
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公开(公告)号：US10672499B2
公开(公告)日：2020-06-02
申请号：US16244321
申请日：2019-01-10
Applicant: RayMX Microelectronics, Corp.
Inventor： Shih-Fu Huang , Shu-Min Lin , Jo-Hua Wu , Cheng-Yu Chen
Abstract: A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit. The voltage supply circuit supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is configured to control an operation of the flash memory. The current sensing circuit is configured to measure the current consumed by the flash memory during its operation, and output a current value. The processor is configured to output a control signal based on the current value. Therefore, the flash memory controller can instantly obtain a current value consumed during the operation of flash memory, and determine, based on the current value, whether the flash memory runs normally. A storage apparatus having the flash memory controller can instantly determine whether the flash memory runs normally.
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公开(公告)号：US10817437B2
公开(公告)日：2020-10-27
申请号：US16243748
申请日：2019-01-09
Applicant: RayMX Microelectronics, Corp.
Inventor： Cheng-Yu Chen , Chih-Ching Chien
Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.
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