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公开(公告)号：US12131043B2
公开(公告)日：2024-10-29
申请号：US18356281
申请日：2023-07-21
Applicant: RAYMX Microelectronics Corp.
Inventor： Zhao-Yao Hu , Shuai Lin , Zhi-Fan Liang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0622 , G06F3/0683
Abstract: A method and a memory controller for accessing a plurality of memories are provided. The method includes sorting a plurality of blocks of a plurality of memories to correspond to a plurality of disk logical addresses that are sequentially sorted. The plurality of blocks of the plurality of memories include M first blocks of a first memory and N second blocks of a second memory, where M and N are each an integer greater than 1, and the M first blocks of the first memory and the N second blocks of the second memory in the plurality of disk logical addresses are sorted in a non-sequential successive order.
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公开(公告)号：US12093549B2
公开(公告)日：2024-09-17
申请号：US17938707
申请日：2022-10-07
Applicant: RayMX Microelectronics, Corp.
Inventor： Hui Wang , Chun Yan Tang , Lin Su
CPC classification number: G06F3/064 , G06F12/0253 , G06F3/0604 , G06F3/0679
Abstract: Disclosed are a method for managing data and a storage device thereof. The storage device includes at least one memory including a plurality of planes, each plane includes a plurality of blocks, and peer blocks in different planes are belonged to operate in a multi-plane mode. The plurality of blocks are detected to find a unavailable block. Then, available blocks corresponding to the unavailable block in planes other than the plane where the unavailable block is located are marked as backup blocks that do not operate in the multi-plane mode. A first block with effective data is selected from the plurality of blocks operating in the multi-plane mode. Data of the first block is moved to a backup block in the same plane.
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公开(公告)号：US12093534B2
公开(公告)日：2024-09-17
申请号：US17932309
申请日：2022-09-15
Applicant: RayMX Microelectronics, Corp.
Inventor： Yinghui Fu , Yunlu Zhang , Hao Li
IPC: G06F3/06 , G06F12/0875
CPC classification number: G06F3/0619 , G06F3/0652 , G06F3/0653 , G06F3/0673 , G06F12/0875 , G06F2212/1032
Abstract: Disclosed are a method for inheriting a defect block table and a storage device thereof. The method applied to a controller of a storage device includes the steps of: storing an original defect block table in a first storage location of a storage module of the storage device, wherein the original defect block table records defect block information of each plane of the storage module; and in response to a low-level format operation being performed on the storage device, reading the original defect block table, and executing a adaptive inheritance procedure based on a multi-plane mode in which the storage device operates, to generate and store a system defect block table in a second storage location of the storage module, wherein the system defect block table records defect block information corresponding to the multi-plane mode.
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公开(公告)号：US20230205441A1
公开(公告)日：2023-06-29
申请号：US17938707
申请日：2022-10-07
Applicant: RayMX Microelectronics, Corp.
Inventor： HUI WANG , CHUN YAN TANG , LIN SU
CPC classification number: G06F3/064 , G06F12/0253 , G06F3/0604 , G06F3/0679
Abstract: Disclosed are a method for managing data and a storage device thereof. The storage device includes at least one memory including a plurality of planes, each plane includes a plurality of blocks, and peer blocks in different planes are belonged to operate in a multi-plane mode. The plurality of blocks are detected to find a unavailable block. Then, available blocks corresponding to the unavailable block in planes other than the plane where the unavailable block is located are marked as backup blocks that do not operate in the multi-plane mode. A first block with effective data is selected from the plurality of blocks operating in the multi-plane mode. Data of the first block is moved to a backup block in the same plane.
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公开(公告)号：US20220156074A1
公开(公告)日：2022-05-19
申请号：US17135088
申请日：2020-12-28
Applicant: RAYMX Microelectronics Corp.
Inventor： SHUAI LIN , ZHAOYAO HU
Abstract: An electronic device includes a memory, a processor, and functional hardware. The memory includes a queue. The processor is configured to write a processing instruction into a target area of the queue. The functional hardware is configured to read the processing instruction from the target area and reserve the target area. The functional hardware generates a completion message according to the processing instruction, and writes the completion message into the target area after the processing instruction is executed. The completion message corresponds to the processing instruction.
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Patent Agency Ranking
公开(公告)号：US20220100408A1
公开(公告)日：2022-03-31
申请号：US17386351
申请日：2021-07-27
Applicant: RayMX Microelectronics Corp.
Inventor： YINGHUI FU , XIN LIU
IPC: G06F3/06
Abstract: Disclosed is a method for maintaining operation log information stored in a non-volatile memory of a storage device. The method includes the steps of: configuring a buffer area of a volatile memory; caching the operation log information into the buffer area; writing the operation log information stored in the buffer area into a predetermined storage area of the non-volatile memory; repeatedly updating the operation log information to the predetermined storage area; and initializing the storage device, which includes the following steps of enabling a watchdog timer in a controller; fetching the latest operation log information by reading the predetermined storage area when the watchdog timer counts a predetermined time and the storage device does not complete the initialization; configuring the storage device to perform a force low-level formatting after the latest operation log information is fetched; and disabling the watchdog timer when the storage device completes the initialization.
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公开(公告)号：US20210389882A1
公开(公告)日：2021-12-16
申请号：US17107983
申请日：2020-12-01
Applicant: RayMX Microelectronics Corp.
Inventor： Yufeng Zhou , SHUANGXI CHEN
IPC: G06F3/06
Abstract: Disclosed is a storage device and a low-level formatting method therefor. The low-level formatting method includes: searching whether an RDT result or firmware storage information is stored in storage blocks of the storage device; determining whether a number of P/E cycles and a TBW of the storage device are recorded in a P/E cycle record and a TBW record included in at least one of the RDT result and the firmware storage information if at least one of the RDT result and the firmware storage information is stored; setting values of the P/E cycles and the TBW to zero if the RDT result and the firmware storage information are not stored or the P/E cycles and the TBW are not recorded in the P/E cycle record and the TBW record.
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公开(公告)号：US10852991B1
公开(公告)日：2020-12-01
申请号：US16548934
申请日：2019-08-23
Applicant: RAYMX Microelectronics Corp.
Inventor： Min-Yan Ciou , Cheng-Yu Chen
IPC: G06F3/06
Abstract: A memory controller includes an interface circuit and a control circuit. The interface circuit is configured to communicate with a host device. When the control circuit finishes executing N commands from the host device, the memory controller notifies the host device to release corresponding memory in the host device corresponding to the N commands, and N is a positive integer. The control circuit compares a data transmission speed of the interface circuit with a predetermined value to generate a comparison result, and the control circuit adjusts a value of N based on the comparison result.
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公开(公告)号：US10776288B2
公开(公告)日：2020-09-15
申请号：US16537692
申请日：2019-08-12
Applicant: RayMX Microelectronics, Corp.
Inventor： Cheng-Yu Chen , Chih-Ching Chien
Abstract: The present invention discloses a memory control device and method compatible to multiple types of interface the memory control device comprises: a multi-interface physical layer circuit configured to couple to a host, to receive a differential signal from the host, to detect at least one of characteristics of the differential signal to generate a physical layer output signal and to generate a physical layer output signal according to a detected result, wherein a frequency of the differential signal is higher than hundreds of KHz; and a processing circuit, coupled between the multi-interface physical layer circuit and a memory module, configured to receive the physical layer output signal from the multi-interface physical layer circuit, to determine the differential signal complies with one of a specification of an first type of interface and that of a second type of interface according to the physical layer output signal, and to adapt an operation mode of the memory control device to one of the multiple types of interface according to a determined result; wherein the memory control device operates in the adapted operation mode to receive at least one access command from the host to access the memory module.
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公开(公告)号：US20240241837A1
公开(公告)日：2024-07-18
申请号：US18359006
申请日：2023-07-26
Applicant: RAYMX Microelectronics Corp.
Inventor： YU ZHANG , YONG-PENG JING
CPC classification number: G06F12/1408 , G06F11/1004
Abstract: A data encryption and decryption system and a data encryption and decryption method for the same are provided. The system includes a memory controlling circuit and an encryption and decryption circuit. In write operation, the encryption and decryption circuit executes an encryption algorithm on write address to obtain first seed data, executes a first scrambling process on initial write data to generate first scrambled data, and executes a second scrambling process on the first scrambled data according to common seed data, so as to generate encrypted write data. The memory controlling circuit writes the encrypted write data into a memory unit according to the write address.
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