公开(公告)号：US09299857B2

公开(公告)日：2016-03-29

申请号：US14309731

申请日：2014-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Ying-Chieh Tsai

IPC: H01L29/66 ,  H01L29/808 ,  H02M3/335 ,  H01L29/06

CPC classification number: H01L29/808 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H02M1/10 ,  H02M1/36 ,  H02M3/33507 ,  H02M2001/0006

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first heavily-doped region formed in the substrate and having the first conductivity type, a second heavily-doped region formed in the substrate and having the first conductivity type, and an embedded layer formed in the substrate and separated from the first and second heavily-doped regions. The embedded layer has a second conductivity type different from the first conductivity type. A portion of the embedded layer is beneath the first heavily-doped region. A third heavily-doped region is formed in the substrate, between the first and second heavily-doped regions, and contacting the embedded layer, and has the second conductivity type.

Abstract translation: 半导体器件包括具有第一导电类型的衬底，形成在衬底中并且具有第一导电类型的第一重掺杂区域，形成在衬底中并且具有第一导电类型的第二重掺杂区域，以及嵌入层 形成在衬底中并与第一和第二重掺杂区分离。 嵌入层具有不同于第一导电类型的第二导电类型。 嵌入层的一部分在第一重掺杂区域之下。 第三重掺杂区域形成在衬底中，在第一和第二重掺杂区域之间，并与嵌入层接触，并且具有第二导电类型。

公开(公告)号：US20150333052A1

公开(公告)日：2015-11-19

申请号：US14275995

申请日：2014-05-13

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Hsin-Liang Chen

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0277 ,  H01L27/0266 ,  H01L27/0629 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7818

Abstract: A semiconductor structure and an electrostatic discharge protection circuit are disclosed. The semiconductor structure includes a device structure comprising a first well region, a second well region, a source, a drain, an extending doped region, and a gate structure. The second well region has conductivity type opposite to a conductivity type of the first well region. The drain has a conductivity type same as a conductivity type of the source. The source and the drain are formed in the first well region and the second well region respectively. The extending doped region is adjoined with drain and extended under the drain. The extending doped region has a conductivity type same as the conductivity type of the drain. The gate structure is on the first well region.

Abstract translation: 公开了半导体结构和静电放电保护电路。 半导体结构包括包括第一阱区，第二阱区，源极，漏极，延伸掺杂区域和栅极结构的器件结构。 第二阱区具有与第一阱区的导电类型相反的导电类型。 漏极具有与源极的导电类型相同的导电类型。 源极和漏极分别形成在第一阱区域和第二阱区域中。 扩散掺杂区域与漏极相邻并在漏极下延伸。 扩散掺杂区域具有与漏极的导电类型相同的导电类型。 栅极结构位于第一阱区域。

公开(公告)号：US09064955B2

公开(公告)日：2015-06-23

申请号：US14076877

申请日：2013-11-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7835 ,  H01L29/7838

Abstract: A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.

Abstract translation: 半导体器件包括源极区域，漏极区域和源极区域与漏极区域之间的漂移区域。 分离栅极设置在漂移区域的一部分上，并且在源极和漏极区域之间。 分离栅极包括由栅极氧化物层隔开的第一和第二栅电极。 自对准RESURF区域设置在栅极和漏极区域之间的漂移区域内。 包括上多晶硅层的PI栅极结构设置在漏极区附近，使得上多晶硅层可以用作形成双RESURF结构的硬掩模，从而允许双RESURF结构的自对准。

公开(公告)号：US09041142B2

公开(公告)日：2015-05-26

申请号：US13710505

申请日：2012-12-11

Applicant: Macronix International Co., Ltd.

Inventor： Ying-Chieh Tsai ,  Wing-Chor Chan ,  Jeng Gong

IPC: H01L29/739

CPC classification number: H01L29/7393

Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region, a fourth doped region and a first gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The first doped region is surrounded by the second doped region. The third doped region has the first type conductivity. The fourth doped region has the second type conductivity. The first gate structure is on the second doped region. The third doped region and the fourth doped region are in the second doped region and the first doped region on opposing sides of the first gate structure respectively.

Abstract translation: 提供了一种半导体器件及其操作方法。 半导体结构包括第一掺杂区，第二掺杂区，第三掺杂区，第四掺杂区和第一栅结构。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性。 第一掺杂区被第二掺杂区围绕。 第三掺杂区域具有第一类型的导电性。 第四掺杂区具有第二类型的导电性。 第一栅极结构在第二掺杂区上。 第三掺杂区域和第四掺杂区域分别位于第二掺杂区域和位于第一栅极结构的相对侧上的第一掺杂区域。

公开(公告)号：US20150140764A1

公开(公告)日：2015-05-21

申请号：US14600305

申请日：2015-01-20

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Shyi-Yuan Wu

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/08 ,  H01L21/311 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/225 ,  H01L21/265 ,  H01L21/26546 ,  H01L21/31111 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.

Abstract translation: 一种半导体器件，特别是由漂移区域中的掺杂浅漏极注入限定的延伸漏极金属氧化物半导体（ED-MOS）器件。 例如，扩展漏极n沟道金属氧化物半导体（ED-NMOS）器件由漂移区域中的n掺杂浅漏极（NDD）注入限定。 该器件的特征还在于导电层部分由薄氧化物层与衬底分离，另一部分由厚/薄的氧化物层分离。 还提供了制造具有漂移区域的掺杂浅漏极注入的半导体器件，特别是ED-NMOS器件的方法。 还提供了一种用于制造部分穿过薄氧化物层并且在另一部分跨越厚/薄氧化物层设置的导电层的方法。

公开(公告)号：US20140253224A1

公开(公告)日：2014-09-11

申请号：US13784886

申请日：2013-03-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wing-Chor Chan ,  Hsin-Liang Chen

IPC: H01L27/02 ,  G05F1/618 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L27/027 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/7816 ,  H01L29/7821 ,  H01L29/7835 ,  H01L29/861

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Abstract translation: 提供半导体元件及其制造方法及其操作方法。 半导体元件包括衬底，第一阱，第一重掺杂区，至少第二重掺杂区，栅极层，第三重掺杂区和第四重掺杂区。 第一阱和第三重掺杂区域设置在衬底上。 第一和第四重掺杂区域设置在第一阱中。 第二重掺杂区域设置在第一重掺杂区域中。 栅极层设置在第一阱上。 具有第一类型掺杂的第一，第三和第四重掺杂区彼此分离。 第一阱和第二重掺杂区域具有与第一类型掺杂互补的第二类型掺杂。

公开(公告)号：US20140232513A1

公开(公告)日：2014-08-21

申请号：US14261478

申请日：2014-04-25

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Li-Fan Chen

IPC: H01L49/02 ,  H01L27/24 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L27/0266 ,  H01L27/0629 ,  H01L27/24 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/808

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract translation: 公开了一种包括衬底，有源器件，场氧化物层和多晶硅电阻器的半导体结构。 有源器件形成在衬底的表面区域中。 有源器件具有第一掺杂区域，第二掺杂区域和第三掺杂区域。 第二掺杂区域设置在第一掺杂区域上。 第一掺杂区域在第二和第三掺杂区域之间。 第一掺杂区域具有第一类型的导电性。 第三掺杂区域具有第二类型的导电性。 第一类和第二类电导率不同。 场氧化物层设置在第三掺杂区域的一部分上。 多晶硅电阻器设置在场氧化物层上并电连接到第三掺杂区域。

公开(公告)号：US20140152349A1

公开(公告)日：2014-06-05

申请号：US13690597

申请日：2012-11-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Ling Hung ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC: H01L23/60 ,  H03K17/06 ,  H01L21/20

CPC classification number: H03K17/063 ,  H01L27/0259

Abstract: A semiconductor device, a manufacturing method thereof and an operating method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer. The first and the second wells are disposed on the substrate. The first and the third heavily doping regions, which are separated from each other, are disposed in the first well, and the second heavily doping region is disposed in the second well. The electrode layer is disposed on the first well. Each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping. Each of the substrate, the first well, and the third heavily doping region has a second type doping, which is complementary to the first type doping.

Abstract translation: 提供了一种半导体器件及其制造方法及其操作方法。 半导体器件包括衬底，第一阱，第二阱，第一重掺杂区，第二重掺杂区，第三重掺杂区和电极层。 第一和第二阱设置在基板上。 彼此分离的第一和第三重掺杂区域设置在第一阱中，并且第二重掺杂区域设置在第二阱中。 电极层设置在第一阱上。 第二阱，第一重掺杂区和第二重掺杂区中的每一个具有第一类掺杂。 衬底，第一阱和第三重掺杂区域中的每一个具有与第一类型掺杂互补的第二类型掺杂。

公开(公告)号：US09786651B2

公开(公告)日：2017-10-10

申请号：US15045414

申请日：2016-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ying-Chieh Tsai ,  Wing-Chor Chan

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/0603 ,  H01L29/866

Abstract: An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

公开(公告)号：US09349830B2

公开(公告)日：2016-05-24

申请号：US13784886

申请日：2013-03-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wing-Chor Chan ,  Hsin-Liang Chen

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74 ,  H01L29/749 ,  H01L29/861 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/66477 ,  H01L27/027 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/7816 ,  H01L29/7821 ,  H01L29/7835 ,  H01L29/861

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Abstract translation: 提供半导体元件及其制造方法及其操作方法。 半导体元件包括衬底，第一阱，第一重掺杂区，至少第二重掺杂区，栅极层，第三重掺杂区和第四重掺杂区。 第一阱和第三重掺杂区域设置在衬底上。 第一和第四重掺杂区域设置在第一阱中。 第二重掺杂区域设置在第一重掺杂区域中。 栅极层设置在第一阱上。 具有第一类型掺杂的第一，第三和第四重掺杂区彼此分离。 第一阱和第二重掺杂区域具有与第一类型掺杂互补的第二类型掺杂。