公开(公告)号：US08785988B1

公开(公告)日：2014-07-22

申请号：US13740006

申请日：2013-01-11

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Li-Fan Chen ,  Chen-Yuan Lin

IPC: H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0705 ,  H01L27/0617 ,  H01L27/085 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/7816 ,  H01L29/808

Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

Abstract translation: 提供包括高压（HV）n型金属氧化物半导体（NMOS）嵌入式HV结栅极场效应晶体管（JFET）的半导体器件。 具有嵌入式HV JFET的HV NMOS可以包括根据第一示例性实施例的衬底，与衬底相邻设置的N型阱区，邻近N型阱区设置的P型阱区，以及第一 以及邻近N型阱和P型阱区的相对侧设置的第二N +掺杂区。 P型阱区域可以包括P +掺杂区域，第三N +掺杂区域和栅极结构，第三N +掺杂区域介于P +掺杂区域和栅极结构之间。

公开(公告)号：US20140266407A1

公开(公告)日：2014-09-18

申请号：US13868134

申请日：2013-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Li-Fan Chen ,  Wing-Chor Chan ,  Jeng Gong

IPC: H01L29/735 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/6625

Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Abstract translation: 提供了一种双极结型晶体管及其操作方法及其制造方法。 双极结晶体管包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域包括在第一掺杂区域中形成的阱区，其具有与第一类型导电性相反的第二类型导电性，并且通过第一掺杂区彼此分离。 第三掺杂区域具有第一类型的导电性。 第三掺杂区域形成在阱区域中或在阱区域之间的第一掺杂区域中。

公开(公告)号：US09306043B2

公开(公告)日：2016-04-05

申请号：US13868134

申请日：2013-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Li-Fan Chen ,  Wing-Chor Chan ,  Jeng Gong

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/6625

Abstract: A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions.

Abstract translation: 提供了一种双极结型晶体管及其操作方法及其制造方法。 双极结晶体管包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域包括在第一掺杂区域中形成的阱区，其具有与第一类型导电性相反的第二类型导电性，并且通过第一掺杂区彼此分离。 第三掺杂区域具有第一类型的导电性。 第三掺杂区域形成在阱区域中或在阱区域之间的第一掺杂区域中。

公开(公告)号：US20140197466A1

公开(公告)日：2014-07-17

申请号：US13740006

申请日：2013-01-11

Applicant: MACRONIX INTERNATIONAL CO., LTD

Inventor： Wing-Chor Chan ,  Li-Fan Chen ,  Chen-Yuan Lin

IPC: H01L27/06

CPC classification number: H01L27/0705 ,  H01L27/0617 ,  H01L27/085 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/7816 ,  H01L29/808

Abstract: A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

Abstract translation: 提供包括高压（HV）n型金属氧化物半导体（NMOS）嵌入式HV结栅极场效应晶体管（JFET）的半导体器件。 具有嵌入式HV JFET的HV NMOS可以包括根据第一示例性实施例的衬底，与衬底相邻设置的N型阱区，邻近N型阱区设置的P型阱区，以及第一 以及邻近N型阱和P型阱区的相对侧设置的第二N +掺杂区。 P型阱区域可以包括P +掺杂区域，第三N +掺杂区域和栅极结构，第三N +掺杂区域介于P +掺杂区域和栅极结构之间。

公开(公告)号：US09054026B2

公开(公告)日：2015-06-09

申请号：US14261478

申请日：2014-04-25

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Li-Fan Chen

IPC: H01L27/02 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/808 ,  H01L29/78 ,  H01L27/06 ,  H01L27/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L27/0266 ,  H01L27/0629 ,  H01L27/24 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/808

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract translation: 公开了一种包括衬底，有源器件，场氧化物层和多晶硅电阻器的半导体结构。 有源器件形成在衬底的表面区域中。 有源器件具有第一掺杂区域，第二掺杂区域和第三掺杂区域。 第二掺杂区域设置在第一掺杂区域上。 第一掺杂区域在第二和第三掺杂区域之间。 第一掺杂区域具有第一类型的导电性。 第三掺杂区域具有第二类型的导电性。 第一类和第二类电导率不同。 场氧化物层设置在第三掺杂区域的一部分上。 多晶硅电阻器设置在场氧化物层上并电连接到第三掺杂区域。

公开(公告)号：US20140232513A1

公开(公告)日：2014-08-21

申请号：US14261478

申请日：2014-04-25

Applicant: Macronix International Co., Ltd.

Inventor： Wing-Chor Chan ,  Li-Fan Chen

IPC: H01L49/02 ,  H01L27/24 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L27/0266 ,  H01L27/0629 ,  H01L27/24 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/808

Abstract: A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area.

Abstract translation: 公开了一种包括衬底，有源器件，场氧化物层和多晶硅电阻器的半导体结构。 有源器件形成在衬底的表面区域中。 有源器件具有第一掺杂区域，第二掺杂区域和第三掺杂区域。 第二掺杂区域设置在第一掺杂区域上。 第一掺杂区域在第二和第三掺杂区域之间。 第一掺杂区域具有第一类型的导电性。 第三掺杂区域具有第二类型的导电性。 第一类和第二类电导率不同。 场氧化物层设置在第三掺杂区域的一部分上。 多晶硅电阻器设置在场氧化物层上并电连接到第三掺杂区域。