公开(公告)号：US20240055512A1

公开(公告)日：2024-02-15

申请号：US18446281

申请日：2023-08-08

Applicant: Monolithic Power Systems, Inc.

Inventor： Vipindas Pala ,  Sauvik Chowdhury

IPC: H01L29/78 ,  H01L29/808 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7803 ,  H01L29/808 ,  H01L29/1058 ,  H01L29/0623 ,  H01L29/7813

Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

公开(公告)号：US20240055473A1

公开(公告)日：2024-02-15

申请号：US18446302

申请日：2023-08-08

Applicant: Monolithic Power Systems, Inc.

Inventor： Vipindas Pala ,  Sauvik Chowdhury

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L29/7813 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/66734

Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

公开(公告)号：US11869982B2

公开(公告)日：2024-01-09

申请号：US17975356

申请日：2022-10-27

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/808 ,  H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

公开(公告)号：US20220344326A1

公开(公告)日：2022-10-27

申请号：US17239333

申请日：2021-04-23

Applicant: MONOLITHIC POWER SYSTEMS,INC.

Inventor： Vipindas Pala

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/808

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

公开(公告)号：US20240055511A1

公开(公告)日：2024-02-15

申请号：US18446130

申请日：2023-08-08

Applicant: Monolithic Power Systems, Inc.

Inventor： Vipindas Pala ,  Sauvik Chowdhury

IPC: H01L29/78 ,  H01L29/808 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7803 ,  H01L29/808 ,  H01L29/1058 ,  H01L29/0623 ,  H01L29/7813

Abstract: A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

公开(公告)号：US20220406601A1

公开(公告)日：2022-12-22

申请号：US17751424

申请日：2022-05-23

Applicant: Monolithic Power Systems, Inc.

Inventor： Sudarsan Uppili ,  Vipindas Pala ,  Carl Johnson ,  Chan Wu ,  John Trepl II

IPC: H01L21/268 ,  H01L21/3065 ,  H01L21/304

Abstract: A semiconductor wafer processing method, having: ablating a back side of a semiconductor wafer with a laser ablation process; and etching the back side of the semiconductor wafer with an etching process; wherein the laser ablation process forms a pattern in the back side of the semiconductor wafer; wherein the etching process preserves the pattern in the back side of the semiconductor wafer.

公开(公告)号：US12283482B2

公开(公告)日：2025-04-22

申请号：US17701088

申请日：2022-03-22

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L21/02 ,  H10D12/01 ,  H10D30/01 ,  H10D62/832

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

公开(公告)号：US12206028B2

公开(公告)日：2025-01-21

申请号：US18073361

申请日：2022-12-01

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala

IPC: H01L29/808 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

公开(公告)号：US20240072160A1

公开(公告)日：2024-02-29

申请号：US18454362

申请日：2023-08-23

Applicant: Monolithic Power Systems, Inc.

Inventor： Haifeng Yang ,  Zhiyong Chen ,  Vipindas Pala ,  Joel McGregor ,  Zeqiang Yao

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/16 ,  H01L29/808

CPC classification number: H01L29/66893 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/808

Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a silicon carbide substrate, trench structures, mesa structures, a first oxide layer, a conductive layer, a second oxide layer, a dielectric layer, and an insulation layer. The trench structures are formed on a surface of the silicon carbide substrate. Each trench structure has sidewalls and a bottom, and each respective mesa structure is formed between the respective adjacent trench structures. The first oxide layer is formed on the sidewalls of the trench structures. The conductive layer is formed on the bottom of the trench structures and on a top surface of each mesa structure. The second oxide layer is formed on the first oxide layer and the conductive layer. The dielectric layer is formed on the second oxide layer. The insulation layer is formed on the dielectric layer.

公开(公告)号：US11545585B2

公开(公告)日：2023-01-03

申请号：US16999942

申请日：2020-08-21

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/78 ,  H01L29/808 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.