公开(公告)号：US20220406601A1

公开(公告)日：2022-12-22

申请号：US17751424

申请日：2022-05-23

Applicant: Monolithic Power Systems, Inc.

Inventor： Sudarsan Uppili ,  Vipindas Pala ,  Carl Johnson ,  Chan Wu ,  John Trepl II

IPC: H01L21/268 ,  H01L21/3065 ,  H01L21/304

Abstract: A semiconductor wafer processing method, having: ablating a back side of a semiconductor wafer with a laser ablation process; and etching the back side of the semiconductor wafer with an etching process; wherein the laser ablation process forms a pattern in the back side of the semiconductor wafer; wherein the etching process preserves the pattern in the back side of the semiconductor wafer.

公开(公告)号：US11682722B2

公开(公告)日：2023-06-20

申请号：US17529747

申请日：2021-11-18

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/808 ,  H01L29/06

CPC classification number: H01L29/7803 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/8083

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

公开(公告)号：US20220059706A1

公开(公告)日：2022-02-24

申请号：US16999942

申请日：2020-08-21

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/808 ,  H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L21/04

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

公开(公告)号：US11869982B2

公开(公告)日：2024-01-09

申请号：US17975356

申请日：2022-10-27

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/808 ,  H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

公开(公告)号：US12283482B2

公开(公告)日：2025-04-22

申请号：US17701088

申请日：2022-03-22

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L21/02 ,  H10D12/01 ,  H10D30/01 ,  H10D62/832

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

公开(公告)号：US11545585B2

公开(公告)日：2023-01-03

申请号：US16999942

申请日：2020-08-21

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： Vipindas Pala ,  Sudarsan Uppili

IPC: H01L29/78 ,  H01L29/808 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.