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公开(公告)号：US12300297B1
公开(公告)日：2025-05-13
申请号：US17817937
申请日：2022-08-05
Applicant: Kepler Computing Inc.
Inventor： Rajeev Kumar Dokania , Mustansir Yunus Mukadam , Noriyuki Sato , Tanay Gosavi , Niloy Mukherjee , Amrita Mathuriya , Sasikanth Manipatruni
IPC: G11C11/22
Abstract: A memory is described having a plurality of bit-cells organized in a row or column. An individual bit-cell of the plurality of bit-cells includes an access transistor and a plurality of capacitors. A word-line is positioned under the access transistor, wherein the access transistor is controllable by the word-line, whereas the plurality of capacitors is positioned above the access transistor. The individual bit-cell has an individual boundary which substantially abuts a neighboring bit-cell in the row or column such that there is no dummy bit-cell between individual bit-cell and the neighboring bit-cell.
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公开(公告)号：US20240276735A1
公开(公告)日：2024-08-15
申请号：US18448918
申请日：2023-08-12
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H10B53/30 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05541 , H01L2224/05557 , H01L2224/05686 , H01L2224/08145 , H01L2224/80931 , H01L2924/04941 , H01L2924/04953
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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3.发明公开公开(公告)号：US20240276734A1
公开(公告)日：2024-08-15
申请号：US18448917
申请日：2023-08-12
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H10B53/20 , H01L28/55 , H01L28/91 , H01L28/92 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H10B51/20
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US20240274651A1
公开(公告)日：2024-08-15
申请号：US18448852
申请日：2023-08-11
Applicant: Kepler Computing Inc.
Inventor： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC classification number: H01L28/60 , H01L24/32 , H01L28/55 , H01L2224/32145
Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US12029043B1
公开(公告)日：2024-07-02
申请号：US17552330
申请日：2021-12-15
Applicant: Kepler Computing Inc.
Inventor： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC: H10B53/30
CPC classification number: H10B53/30
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240211872A1
公开(公告)日：2024-06-27
申请号：US18358545
申请日：2023-07-25
Applicant: Kepler Computing Inc.
Inventor： Sasikanth Manipatruni , Niloy Mukherjee , Noriyuki Sato , Tanay Gosavi , Somilkumar J. Rathi , James David Clarkson , Rajeev Kumar Dokania , Debo Olaosebikan , Amrita Mathuriya
CPC classification number: G06Q10/087 , G06Q30/04 , G16C20/70
Abstract: A method for monetizing ferroelectric process development is described. In at least one embodiment, the method comprises procuring a target material based on a model driven selection which is based on charge, mass and magnetic moment, and/or mass of the atomic constituents of the target material. The method further comprises applying the target material to a fabrication process to build a ferroelectric device. The method further comprises generating a notification indicative of procurement of the target material and application of the target material. The method further comprises electronically transmitting the notification to a customer, wherein the notification includes an invoice having a line item associated with a cost of the procuring of the target material and application of the target material.
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公开(公告)号：US11955512B1
公开(公告)日：2024-04-09
申请号：US17552266
申请日：2021-12-15
Applicant: Kepler Computing Inc.
Inventor： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC: H01L21/321 , H01L21/768 , H01L49/02
CPC classification number: H01L28/91 , H01L21/3212 , H01L21/76843 , H01L28/92
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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公开(公告)号：US11871584B1
公开(公告)日：2024-01-09
申请号：US17553475
申请日：2021-12-16
Applicant: Kepler Computing Inc.
Inventor： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC classification number: H10B53/30
Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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公开(公告)号：US11854593B2
公开(公告)日：2023-12-26
申请号：US17478850
申请日：2021-09-17
Applicant: Kepler Computing, Inc.
Inventor： Noriyuki Sato , Tanay Gosavi , Niloy Mukherjee , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
IPC: H01L23/522 , H01L23/532 , H01L23/538 , G11C11/22 , H03K19/185 , H01L21/768 , H01L49/02 , H10B53/30 , H01L23/535 , H10B53/20
CPC classification number: G11C11/221 , H01L21/76802 , H01L21/76805 , H01L21/76831 , H01L21/76895 , H01L23/5226 , H01L23/535 , H01L23/5381 , H01L23/5386 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L28/55 , H01L28/60 , H01L28/65 , H03K19/185 , H10B53/20 , H10B53/30
Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
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10.发明公开公开(公告)号：US20230246062A1
公开(公告)日：2023-08-03
申请号：US17649534
申请日：2022-01-31
Applicant: Kepler Computing Inc.
Inventor： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC: H01L49/02 , H01L21/324 , H01L21/768 , H01L27/11507 , H01L45/00
CPC classification number: H01L28/57 , H01L21/324 , H01L21/76832 , H01L27/11507 , H01L28/65 , H01L28/75 , H01L45/147
Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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