公开(公告)号：US12294370B1

公开(公告)日：2025-05-06

申请号：US17467100

申请日：2021-09-03

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Ikenna Odinaka ,  Rajeev Kumar Dokania ,  Rafael Rios ,  Sasikanth Manipatruni

IPC: H03K19/23 ,  H01L49/02

Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

公开(公告)号：US12289894B1

公开(公告)日：2025-04-29

申请号：US17807655

申请日：2022-06-17

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Rafael Rios ,  Amrita Mathuriya ,  Niloy Mukherjee ,  Somilkumar J. Rathi ,  Sasikanth Manipatruni ,  Tanay Gosavi

IPC: H10B53/20 ,  H01L23/522 ,  H01L23/528 ,  H10B53/10 ,  H10B53/30

Abstract: A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

公开(公告)号：US12262543B1

公开(公告)日：2025-03-25

申请号：US18450499

申请日：2023-08-16

Applicant: Kepler Computing Inc.

Inventor： Debraj Guhabiswas ,  Maria Isabel Perez ,  Jason Y. Wu ,  James David Clarkson ,  Gabriel Antonio Paulius Velarde ,  Niloy Mukherjee ,  Noriyuki Sato ,  Amrita Mathuriya ,  Saskikanth Manipatruni ,  Ramamoorthy Ramesh

IPC: H01L21/00 ,  H01L49/02 ,  H10B53/30

Abstract: Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US12190946B1

公开(公告)日：2025-01-07

申请号：US17805664

申请日：2022-06-06

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Mustansir Yunus Mukadam ,  Tanay Gosavi ,  James David Clarkson ,  Neal Reynolds ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: G11C11/22 ,  G11C11/401 ,  G11C11/419

Abstract: A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

公开(公告)号：US20240421229A1

公开(公告)日：2024-12-19

申请号：US18619772

申请日：2024-03-28

Applicant: Kepler Computing Inc.

Inventor： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H10B12/00 ,  H10B53/30

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20240379143A1

公开(公告)日：2024-11-14

申请号：US18781878

申请日：2024-07-23

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Mustansir Yunus Mukadam ,  Erik Unterborn ,  Pramod Kolar ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC: G11C11/22

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

公开(公告)号：US12041785B1

公开(公告)日：2024-07-16

申请号：US17654383

申请日：2022-03-10

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Debo Olaosebikan ,  Tanay Gosavi ,  Noriyuki Sato ,  Sasikanth Manipatruni

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

公开(公告)号：US12022662B1

公开(公告)日：2024-06-25

申请号：US17552321

申请日：2021-12-15

Applicant: Kepler Computing Inc.

Inventor： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12016185B1

公开(公告)日：2024-06-18

申请号：US17552293

申请日：2021-12-15

Applicant: Kepler Computing Inc.

Inventor： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12001266B1

公开(公告)日：2024-06-04

申请号：US17408323

申请日：2021-08-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/32 ,  G06F1/329 ,  G11C5/04 ,  G11C11/00 ,  H01L25/16 ,  G06N20/00

CPC classification number: G06F1/329 ,  G11C5/04 ,  G11C11/005 ,  H01L25/162 ,  G06N20/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2924/1441

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.