公开(公告)号：US11380789B2

公开(公告)日：2022-07-05

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/20

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US09634107B2

公开(公告)日：2017-04-25

申请号：US14285080

申请日：2014-05-22

Applicant: IMEC

Inventor： Brice De Jaeger ,  Marleen Van Hove ,  Stefaan Decoutere ,  Steve Stoffels

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/454 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

公开(公告)号：US20160163695A1

公开(公告)日：2016-06-09

申请号：US14963650

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Niels Posthuma ,  Shuzhen You

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/761 ,  H01L21/22 ,  H01L29/778 ,  H01L21/74

CPC classification number: H01L27/0629 ,  H01L21/761 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/7786

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract translation: 一种集成电路，包括具有源极区的第一III-N晶体管和具有源极区的第二III-N晶体管，两个晶体管单片集成在第一掺杂类型的公共硅衬底上并且通过隔离彼此分离 所述衬底包括在所述第一晶体管下方的第一掺杂类型的阱，所述阱的第一掺杂类型电连接到所述第一晶体管的源极区，并且在所述第二晶体管的下方包括电连接到所述第二晶体管的源极区的第二掺杂型阱， 从而在第一和第二晶体管的源极之间的衬底中形成结二极管。

公开(公告)号：US20140346568A1

公开(公告)日：2014-11-27

申请号：US14285080

申请日：2014-05-22

Applicant: IMEC

Inventor： Brice De Jaeger ,  Marleen Van Hove ,  Stefaan Decoutere

IPC: H01L29/45 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/454 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

Abstract translation: 本公开涉及一种用于制造半导体衬底上的III族氮化物（III-N）器件的无Au欧姆接触的方法以及由其获得的III-N器件。 III-N器件包括缓冲层，沟道层，阻挡层和钝化层。 在沟道层和阻挡层之间的界面处形成2DEG层。 该方法包括在钝化层和阻挡层中形成直到2DEG层的凹槽，并在凹槽中形成无Au金属叠层。 金属叠层包括Ti / Al双层，Ti层覆盖并与凹陷的底部接触，并且覆盖并与Ti层接触的Al层。 Ti层与Al层的厚度比为0.01〜0.1。 在形成金属堆叠之后，进行快速热退火。 可选地，在形成Ti / Al双层之前，可以形成与该凹部接触的硅层。

公开(公告)号：US11094629B2

公开(公告)日：2021-08-17

申请号：US16726120

申请日：2019-12-23

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Steve Stoffels

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/64 ,  H01L29/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L23/367 ,  H01L23/528

Abstract: A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

公开(公告)号：US20200243678A1

公开(公告)日：2020-07-30

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L21/8252 ,  H01L29/778

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US09711601B2

公开(公告)日：2017-07-18

申请号：US14056643

申请日：2013-10-17

Applicant: IMEC

Inventor： Stefaan Decoutere ,  Nicolo Ronchi

IPC: H01L29/417 ,  H01L29/872 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/205 ,  H01L29/40

CPC classification number: H01L29/417 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/66219 ,  H01L29/7787 ,  H01L29/872

Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other.

公开(公告)号：US09431511B2

公开(公告)日：2016-08-30

申请号：US14682958

申请日：2015-04-09

Applicant: IMEC

Inventor： Stefaan Decoutere ,  Silvia Lenci

IPC: H01L29/66 ,  H01L27/06 ,  H01L21/8252 ,  H01L29/872 ,  H01L29/778 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/66431 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/872

Abstract: A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.

公开(公告)号：US20140159118A1

公开(公告)日：2014-06-12

申请号：US14101710

申请日：2013-12-10

Applicant: IMEC

Inventor： Sylvia Lenci ,  Stefaan Decoutere

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/283 ,  H01L21/48 ,  H01L29/778 ,  H01L21/28

CPC classification number: H01L29/66431 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/308 ,  H01L21/4814 ,  H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode.

Abstract translation: 公开了半导体器件及其制造方法。 示例性装置可以包括具有前侧表面和后侧表面的III族氮化物堆叠。 III族氮化物堆叠可以由至少第一层和第二层形成，其间可以形成异质结，从而在第二层中形成二维电子气层。 位于源极和漏极之间的源电极，漏电极和栅极可以形成在前侧表面上，并且可以在前侧表面上的电极上形成绝缘层。 载体衬底可以附着到绝缘层。 导电背板可以形成在背侧表面上。 背板可以直接面对源电极和栅电极，而不是漏电极。

公开(公告)号：US12002680B2

公开(公告)日：2024-06-04

申请号：US17345229

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Niels Posthuma ,  Stefaan Decoutere

IPC: H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/28581 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.