公开(公告)号：US20140211554A1

公开(公告)日：2014-07-31

申请号：US14242495

申请日：2014-04-08

Applicant: Being Advanced Memory Corporation

Inventor： Yuanxing Li ,  Van Butler ,  Ryan Jurasek

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.

公开(公告)号：US20140204667A1

公开(公告)日：2014-07-24

申请号：US14223636

申请日：2014-03-24

Applicant: BEING ADVANCED MEMORY CORPORATION

Inventor： Ryan Jurasek

IPC: G11C13/00

CPC classification number: G11C13/0021 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C29/78 ,  G11C2213/79

Abstract: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.

公开(公告)号：US08908427B1

公开(公告)日：2014-12-09

申请号：US14223761

申请日：2014-03-24

Applicant: Being Advanced Memory Corporation

Inventor： Aaron D. Willey ,  Ryan Jurasek

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/14 ,  G11C11/5678 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.

公开(公告)号：US20140321200A1

公开(公告)日：2014-10-30

申请号：US14223774

申请日：2014-03-24

Applicant: Being Advanced Memory Corporation

Inventor： Aaron D. Willey ,  Ryan Jurasek

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/14 ,  G11C11/5678 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.

Abstract translation: 用于PCM存储器的基于时间的单元解码的方法和系统。 通常，PCM元件电阻越高，读取输出变化的时间就越长。 读取输出改变状态的差分定时而不是读出输出的微分值来确定PCM存储器输出。 在一些单位单端感测实施例中，具有对应于一对相邻逻辑状态的电阻之间的电阻的参考被存储在多个参考单元中; 当大部分参考单元读取输出在投票单位过渡时，“投票”单元发出时钟信号。 定时单元产生不同的二进制输出，取决于数据读取输出或时钟信号是否在定时单元处先改变状态。 基于时间的解码提供了优点，包括改进的温度和漂移弹性，改进的状态辨别，改进的多位PCM的可靠性，以及快速和可靠的感测。

公开(公告)号：US08854875B1

公开(公告)日：2014-10-07

申请号：US14242454

申请日：2014-04-01

Applicant: Being Advanced Memory Corporation

Inventor： Aaron D. Willey ,  Ryan Jurasek

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C7/14 ,  G11C11/5678 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.

公开(公告)号：US20140211555A1

公开(公告)日：2014-07-31

申请号：US14242508

申请日：2014-04-01

Applicant: BEING ADVANCED MEMORY CORPORATION

Inventor： Yuanxing Li ,  Van Butler ,  Ryan Jurasek

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.

公开(公告)号：US20130336051A1

公开(公告)日：2013-12-19

申请号：US13869486

申请日：2013-04-24

Applicant: Being Advanced Memory Corporation

Inventor： Ryan Jurasek ,  Aaron D. Willey

IPC: G11C13/00

CPC classification number: G11C13/0021 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C29/78 ,  G11C2213/79

Abstract: Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful.

Abstract translation: 使用多位PCM的系统，包括存储器系统，以及用于操作这些系统的方法。 可以使用具有已知状态的多位PCM存储器元件的测试来确定立即可用的电压电平是否可以可靠地读取多位PCM。 这可以用于加速驻留在多比特PCM中的存储器状态的可用性，例如，冗余地址存储，其他启动状态信息和非易失性存储器有用的参数。

公开(公告)号：US09036408B1

公开(公告)日：2015-05-19

申请号：US14011327

申请日：2013-08-27

Applicant: Being Advanced Memory Corporation

Inventor： Ryan Jurasek ,  Aaron Willey

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0042

Abstract: Methods, circuits, and systems for phase change memories. A matching bit line, on which no data-containing PCM cells have been selected, is used to cancel out time-dependent current components due to parasitic capacitive and leakage resistance loading of bit lines. This can effectively allow direct comparison of the current from the phase change memory cell to the desired reference current, at a time before the voltage of the first bit line permits stable operations using DC comparison.

Abstract translation: 用于相变存储器的方法，电路和系统。 由于位线的寄生电容和泄漏电阻负载，使用其上没有选择含有数据的PCM单元的匹配位线来消除时间相关的电流分量。 这可以在第一位线的电压允许使用DC比较的稳定操作之前的时刻，有效地允许将来自相变存储器单元的电流直接比较到期望的参考电流。

公开(公告)号：US08830731B2

公开(公告)日：2014-09-09

申请号：US14242508

申请日：2014-04-01

Applicant: Being Advanced Memory Corporation

Inventor： Yuanxing Li ,  Van Butler ,  Ryan Jurasek

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.

公开(公告)号：US08773891B2

公开(公告)日：2014-07-08

申请号：US14011266

申请日：2013-08-27

Applicant: Being Advanced Memory Corporation

Inventor： Yuanxing Li ,  Van Butler ,  Ryan Jurasek

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.