公开(公告)号：US20160190265A1

公开(公告)日：2016-06-30

申请号：US15061912

申请日：2016-03-04

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract translation: 多个栅极沟槽在活性电池区域中形成为半导体衬底。 一个或多个其它沟槽形成在不同的区域中。 每个栅极沟槽在下部具有第一导电材料，在上部具有第二导电材料。 在栅极沟槽中，第一绝缘层将第一导电材料与衬底分离，第二绝缘层将第二导电材料与衬底分开，并且第三绝缘材料分离第一和第二导电材料。 其他沟槽包含下部分中的半U形的第一导电材料的一部分和上部的第二导电材料的一部分。 在其他沟槽中，第三绝缘层分离第一和第二导电材料。 第一绝缘层比第三绝缘层厚，第三绝缘层比第二绝缘层厚。

公开(公告)号：US09281368B1

公开(公告)日：2016-03-08

申请号：US14569276

申请日：2014-12-12

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

Abstract translation: 多个栅极沟槽在活性电池区域中形成为半导体衬底。 一个或多个其它沟槽形成在不同的区域中。 每个栅极沟槽在下部具有第一导电材料，在上部具有第二导电材料。 在栅极沟槽中，第一绝缘层将第一导电材料与衬底分离，第二绝缘层将第二导电材料与衬底分开，并且第三绝缘材料分离第一和第二导电材料。 其他沟槽包含下部分中的半U形的第一导电材料的一部分和上部的第二导电材料的一部分。 在其他沟槽中，第三绝缘层分离第一和第二导电材料。 第一绝缘层比第三绝缘层厚，第三绝缘层比第二绝缘层厚。

公开(公告)号：US09691863B2

公开(公告)日：2017-06-27

申请号：US14681887

申请日：2015-04-08

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hongyong Xue ,  Sik Lui ,  Terence Huang ,  Ching-Kai Lin ,  Wenjun Li ,  Yi Chang Yang ,  Jowei Dun

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US09865694B2

公开(公告)日：2018-01-09

申请号：US15412896

申请日：2017-01-23

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

公开(公告)号：US20170288028A1

公开(公告)日：2017-10-05

申请号：US15623303

申请日：2017-06-14

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hongyong Xue ,  Sik Lui ,  Terence Huang ,  Ching-Kai Lin ,  Wenjun Li ,  Yi Chang Yang ,  Jowei Dun

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US09741808B2

公开(公告)日：2017-08-22

申请号：US15061912

申请日：2016-03-04

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

公开(公告)号：US20170133473A1

公开(公告)日：2017-05-11

申请号：US15412896

申请日：2017-01-23

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

公开(公告)号：US20160300917A1

公开(公告)日：2016-10-13

申请号：US14681887

申请日：2015-04-08

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hongyong Xue ,  Sik Lui ,  Terence Huang ,  Ching-Kai Lin ,  Wenjun Li ,  Yi Chang Yang ,  Jowei Dun

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 本公开的实施例提供了用于沟槽功率MOSFET器件的自对准接触。 该器件具有设置在栅极沟槽中的导电材料上方的氮化物层和每两个相邻接触结构之间的台面的超过部分。 或者，器件在栅极沟槽中的导电材料上方具有氧化物层，并且在每两个相邻的接触结构之间具有台面的上部。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。