公开(公告)号：US09673289B2

公开(公告)日：2017-06-06

申请号：US14880886

申请日：2015-10-12

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Daniel Calafut ,  Madhur Bobde ,  Yeeheng Lee ,  Hong Chang

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/42368 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.

公开(公告)号：US20170133473A1

公开(公告)日：2017-05-11

申请号：US15412896

申请日：2017-01-23

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

公开(公告)号：US20160099325A1

公开(公告)日：2016-04-07

申请号：US14880886

申请日：2015-10-12

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Daniel Calafut ,  Madhur Bobde ,  Yeeheng Lee ,  Hong Chang

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness greater than the first thickness.

Abstract translation: 一种功率MOSFET器件，包括半导体层，形成在所述半导体层中的有源沟槽并且容纳双重氧化物厚度沟槽栅极结构，其中所述沟槽栅极的底部与所述有源沟槽的底部隔离，所述衬底氧化物层具有第一 厚度以及形成在半导体层中的有源沟槽之间的端接沟槽，并且容纳双重氧化物厚度沟槽栅极结构，其中沟槽栅极的底部通过具有第二厚度的衬里氧化物层与端接沟槽的底部隔离 大于第一厚度。

公开(公告)号：US20160099315A1

公开(公告)日：2016-04-07

申请号：US14965009

申请日：2015-12-10

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/36 ,  H01L29/423 ,  H01L29/417 ,  H01L29/739 ,  H01L29/872 ,  H01L29/861 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

公开(公告)号：US20160064551A1

公开(公告)日：2016-03-03

申请号：US14937636

申请日：2015-11-10

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Lui ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC: H01L29/78 ,  H01L23/66 ,  H01L29/10 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US09190478B2

公开(公告)日：2015-11-17

申请号：US14138103

申请日：2013-12-22

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Daniel Calafut ,  Madhur Bobde ,  Yeeheng Lee ,  Hong Chang

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42368 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A method for forming a dual oxide thickness trench gate structure for a power MOSFET includes providing a semiconductor substrate; forming a first trench on a top surface of the substrate; forming a first oxide layer in the first trench where the first oxide layer has a first depth from the bottom of the first trench; forming a dielectric spacer along the sidewall of the first trench and on the first oxide layer; etching the first oxide layer exposed by the dielectric spacer to a second depth from the bottom of the first trench using the dielectric spacer as a mask where the second depth is lower than the first depth; removing the dielectric spacer; and forming a second oxide layer along the sidewall of the first trench above the first oxide layer where the second oxide layer has a thickness thinner than the thickness of the first oxide layer.

Abstract translation: 用于形成用于功率MOSFET的双重氧化物厚度沟槽栅极结构的方法包括提供半导体衬底; 在所述基板的顶表面上形成第一沟槽; 在所述第一沟槽中形成第一氧化物层，其中所述第一氧化物层具有从所述第一沟槽的底部开始的第一深度; 沿着所述第一沟槽的侧壁和所述第一氧化物层形成电介质间隔物; 使用所述电介质间隔物作为所述第二深度低于所述第一深度的掩模，将由所述电介质间隔物暴露的所述第一氧化物层蚀刻到所述第一沟槽的底部的第二深度; 去除介电间隔物; 以及沿着所述第一氧化物层的所述第一沟槽的所述侧壁形成第二氧化物层，其中所述第二氧化物层具有比所述第一氧化物层的厚度更薄的厚度。

公开(公告)号：US09136380B2

公开(公告)日：2015-09-15

申请号：US14329806

申请日：2014-07-11

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与沿着栅极盖的侧壁形成的间隔物自对准。 另外，有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 与自对准源触点结合的两步栅极氧化物允许生产具有深亚微米级的间距的器件。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20150145037A1

公开(公告)日：2015-05-28

申请号：US14606928

申请日：2015-01-27

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Yeeheng Lee ,  Hong Chang ,  Jongoh Kim ,  Sik Lui ,  Hamza Yilmaz ,  Madhur Bobde ,  Daniel Calafut ,  John Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L27/02

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L21/3081 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0292 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。 源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。 另外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20150001616A1

公开(公告)日：2015-01-01

申请号：US14486391

申请日：2014-09-15

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Daniel Calafut ,  Yi Su ,  Jongoh Kim ,  Hong Chang ,  Hamza Yilmaz ,  Daniel S. Ng

IPC: H01L29/872 ,  H01L27/06

CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/06 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872

Abstract: A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

Abstract translation: 肖特基二极管包括形成在半导体层中的第一和第二沟槽，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，其余部分填充有第一介电层。 阱区在第一和第二沟槽之间的半导体层的顶部部分间隔开形成。 在第一和第二沟槽之间的半导体层的顶表面上形成肖特金属层。 肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。 第一和第二沟槽中的沟槽导体层电连接到肖特基二极管的阳极。 在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

公开(公告)号：US20140299914A1

公开(公告)日：2014-10-09

申请号：US14243758

申请日：2014-04-02

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a second semiconductor layer disposed on a first semiconductor layer of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the second semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. The semiconductor device further includes a first dielectric layer formed in the trenches adjacent the first epitaxial layer and a gate electrode disposed in an upper portion of at least some of the trenches above the first dielectric layer and insulated from the sidewalls of the trenches by a gate dielectric layer.

Abstract translation: 使用形成在介质填充沟槽的侧壁上的薄外延层（纳米管）来形成半导体器件。 在一个实施例中，半导体器件形成在第二半导体层中，第二半导体层设置在相反导电类型的第一半导体层上，并且其中形成有沟槽，其中沟槽从第二半导体层的顶表面延伸到底表面。 半导体器件包括形成在沟槽的侧壁上的第一外延层，其中第一外延层基本上与相邻半导体区域电荷平衡。 半导体器件还包括形成在与第一外延层相邻的沟槽中的第一介电层和设置在第一介电层上方至少一些沟槽的上部的栅电极，并且通过栅极与沟槽的侧壁绝缘 电介质层。