公开(公告)号：US08437208B2

公开(公告)日：2013-05-07

申请号：US13430444

申请日：2012-03-26

Applicant: Yoshinori Fujiware

Inventor： Yoshinori Fujiware

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G06F12/06 ,  G11C7/06 ,  G11C8/12 ,  G11C29/785 ,  G11C29/81 ,  G11C29/846

Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.